Hi,
I noticed that when an Rx-FIFO overrun occurs, and thus SR[REF] is high, SPI transfers are stalled if CFGR1[NOSTALL] = '0'. Setting NOSTALL = '1' allows transfers to occur, even if REF = '1'.
When I reference S32K1xx Series Reference Manual, Rev. 12.1, 02/2020, two things come to my mind:
1. The effect of Rx overrun on stalling transfers is not mentioned.
For SR[TEF], the RM clearly mentions that when TEF is set when NOSTALL = '0', transfers will stall:
Indicates a transmit/command FIFO underrun. In master mode when the No Stall CFGR1[NOSTALL] bit is clear (0, transfers will stall when transmit FIFO is empty), the Transmit Error Flag bit cannot set.
The description for REF does not mention such behaviour:
Receive error flag, indicates a receive FIFO overflow.
Simply following the documentation, I would not expect REF to impact SPI transfers and cause a stall.
2. The effect of NOSTALL on Rx overrun stalling is never specified.
For NOSTALL, the RM mentions:
In master mode, the LPSPI will stall transfers when the transmit FIFO is empty, ensuring that no transmit FIFO underrun can occur. Setting the No Stall bit will disable this functionality.
0b - Transfers will stall when the transmit FIFO is empty
1b - Transfers will not stall, allowing transmit FIFO underruns to occur
Again, only the effect of the transmit FIFO is explicitly described here. Reading this documentation, I still don't expect a stall when Rx has overrun.
I recently found S32K144 LPSPI getting stuck in "void LPSPI1_transmit_16bits (uint16_t send)" function which confirmed my suspicion that REF causes a stall, and that NOSTALL can override this behaviour.
Am I correct to assume that this is the intended device operation, and that the documentation is missing in the reference manual?
Kind regards,
Joey van Hummel
