LPI2C behavior on the overrun condition

[james-lee]

Hello team,

Would you please clarify the LPI2C behavior below in the slave mode?

1. Is the 4 depth of Rx FIFO available in the slave mode?

2. If not, in the overrun condition, does the following data overwrite the pending data? or is the following data discarded?

3. If the following data overwrites the pending data, when would it be done? After receiving the last bit of data?

4. If the STOP condition is detected during the data was pending, how does the LPI2C module behave?

Best regards,

James

[danielmartynek]

Hello James,

1.

No, only the master features the FIFO.

danielmartynek_0-1620121651066.png

2 & 3.

This is not specified, but the LPI2C Slave supports clock stretching.

Refer to AN5301 Using LPI2C on KL28, Section 6.2. Configure stall

https://www.nxp.com/docs/en/application-note/AN5301.pdf

Or the S32K1xx RM, rev.13, Section 52.3.3.3 Clock Stretching

In both configurations, the LPI2C Slave stalls the bus (SCL held low) until the data are read and the transfer acknowledged.

4.

If the LPI2C slave receives a STOP condition, the SDF flag is set.

But again, the Master can't send a STOP condition while the bus is being stalled.

danielmartynek_1-1620122243530.png

UM10204 I2C-bus specification and user manual

https://www.nxp.com/docs/en/user-guide/UM10204.pdf

Regards,

Daniel

[bobpaddock]

Is there any code, like a .zip file that goes with AN5301?
All I'm finding is the PDF.