LPI2C: Inverted SCL on S32k144

[ArushThomas]

Hi all,

I was trying to configure an S32k144 as an I2C Master, and seem to have encountered a bug. The SCL waveform is inverted (HIGH when it should be LOW, and vice-versa). I have observed this behaviour on my Oscilloscope;

• pink: SCL
• yellow: SDA

This behaviour is observed in Debug mode, when I disable all breakpoints and let the code run at regular speed.

When I step through the code line-by-line with the Debug features, I observe different behaviour

This is the waveform I had expected at all times.

• The S32k144 is configured as a Master I2C device, and no other devices are present on the bus.
• I am using the LPI2C0 peripheral, on pins PTA3 and PTA2.
  • Pins PTB7 and PTB6 are connected to an External crystal oscillator, so I haven't tested those.
• External 4.7k pull-up resistors are connected to the SCL and SDA signals.
• I have verified open-drain configuration of the pins, and all Clock settings.
• Both the Blocking and Non-Blocking methods provide the same waveforms. [I2C_MasterSendDataBlocking() and I2C_MasterSendData()]

Here's the code;

 

EDIT: Added project "I2C_Reconfig.zip", which produces this issue

[danielmartynek]

Hi @ArushThomas,

The SCL signal is not inverted but shifted.

I could not open your project, because you use an older SDK, unfortunately.

Nevertheless, I could reproduce it with a simple bare-metal code.

We can see the shift when the LPI2C module is operational in active debug mode.

MCR_DBGEN = 0

MCR_DBGEN = 1

If you don't need the module active while the CPU is halted in debug mode, clear DBGEN.

Thank you,

BR, Daniel

[ArushThomas]

Hi @danielmartynek, thanks for your reply!

I've tried to implement your solution, here's my code;

I2C_MasterInit(&i2c1_instance, &i2c1_MasterConfig0);
LPI2C0->MCR |= LPI2C_MCR_DBGEN_MASK; //MCR value is set to 9
//LPI2C0->MCR &= ~LPI2C_MCR_DBGEN_MASK; //MCR value is set to 1
for(;;){
  I2C_MasterSendData(&i2c1_instance, masterTxBuffer, TRANSFER_SIZE, true);
  OSIF_TimeDelay(50);
}

 Probing the waveforms on my scope again, I'm not seeing any difference; the SCL waveform is still Shifted, whether MCR is 9 or 1.

As a sanity check, I set MCR_MEN to 0, to verify I was writing to the correct register. This completely stopped all waveforms, as I had expected. (Master logic is disabled)

Incidentally, I am not facing this issue when I set the Baud Rate to 400kHz; This issue only seems to present itself at 100kHz

Correct waveform observed @400kHz

[danielmartynek]

Hi @ArushThomas,

If the non-blocking API is used (I2C_MasterSendData()), we need to use the I2C_MasterGetTransferStatus() before we can call I2C_MasterSendData() again.

Can you use it?

Thanks,

BR, Daniel

[danielmartynek]

Hi @ArushThomas,

Could you attach the project here so that I can reproduce it?

Is the LPI2C module reporting any error during the test?

Thank you,

BR, Daniel

[ArushThomas]

Sure! I've edited my original post to attach the project .zip file

Is the LPI2C module reporting any error during the test?

I've used the status_t error variable to identify if any function returns an error status. All Init() functions return STATUS_SUCCESS. The I2C_MasterSendDataBlocking() function returns STATUS_I2C_RECEIVED_NACK. I expected this, since there is no Slave on the I2C bus.

The I2C_MasterSendData() function returns STATUS_SUCCESS. I did not expect this, I was expecting NACK again.

Is there some other technique I need to follow, to identify if the LPI2C module reports an error?

[danielmartynek]

Regarding the non-blocking method: The I2C_MasterSendData(),

The function completes before the transfer is finished, it does not block the core during the transfer.

We need to use this API: I2C_MasterGetTransferStatus() to get the expected STATUS_I2C_RECEIVED_NACK

Regards,

Daniel