K310_SPI

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K310_SPI

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hajianik
Senior Contributor I

Hi,

I recently configure the SPI module using the peripheral s tool for s32k310.

there's no slave connected yet however i attempted to test just the MOSI transmit behavior.

to that end I configure the SPI device as seen below:

hajianik_0-1693432619606.png

so I connected the pins to the scope as follows DI MOSI- D2 MISO- D3 CLK and D4 CS and naturally they are floating. so I want to share 2 screen captures with you , the 1st is when everything is as is expected and 2nd is mismatched error laced.

 

hajianik_1-1693433191456.png

Here is the good transfer of 1,2,3,4,5 on MOSI . Notice the yellow curve at the bottom which indicate the analog representation of the the CS.

 

hajianik_2-1693433478726.png

Here is the bad transfer where the CS is toggling randomly however the analog CS looks like the good transfer.

How do you explain this behavior? is it because they're floating and there's no load? in that case why I don't see any glitches on the analog CS.

 

Regards,

Koorosh Hajiani

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davidtosenovjan
NXP TechSupport
NXP TechSupport

I understand you - I have meant whether you have some details about occurrence of mentioned erratic behavior. It is somehow interesting as it does not seem spikes would be regular. Maybe you could double check with oscilloscope if you have some available.

Toggle means CS is negated between every data frame. Keep asserted means that CS stays asserted between data frames but it is supposed to be negated after end of transfer.

Possibly you may see following thread:
https://community.nxp.com/t5/S32K/LPSPI-Chip-Select-always-is-LOW-active-state/m-p/1563159

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Could you explain when you see the bad transfer? According you setting CS is supposed to be keep asserted so I am not sure what exactly you measuring in bad case. Floating pins should not affect it anyhow because outputs are driven by push-pull circuits.

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hajianik
Senior Contributor I

Hi,

Compare  CS  (CHANNELL D4)capture1 to  THE capture 2 CS(CHA D4) . There are glitches on CS  on capture2 when the MOSI values are in error.

I'm sending ( MOSI) THE VALUES 0X01,0X02,0X03,0X04,0x05, 5 BYTES CONTINOUSLY .

The good transfer is when you observe these values on MOSI( BROWN COLOR) AND THE BAD CAPTURE is when these values are in error i.e. capture2.

either option for CS(TOGGLE OR ALWAYS ASSERTED) does not make any difference..

I'm leaning towards the SALEAE SPI  Analyzer tool MAY BE AT FAULT HERE .I'll let you know.

one more question: when we choose the option of toggle vs assert always in configure tool ,

toggle means to assert every 8 bits? and the other option means assert it for the duration of the frame ( in my case 40 bits)

Thanks,

Koorosh

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davidtosenovjan
NXP TechSupport
NXP TechSupport

I understand you - I have meant whether you have some details about occurrence of mentioned erratic behavior. It is somehow interesting as it does not seem spikes would be regular. Maybe you could double check with oscilloscope if you have some available.

Toggle means CS is negated between every data frame. Keep asserted means that CS stays asserted between data frames but it is supposed to be negated after end of transfer.

Possibly you may see following thread:
https://community.nxp.com/t5/S32K/LPSPI-Chip-Select-always-is-LOW-active-state/m-p/1563159

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