Issue with Multiple Channel Range Compare Interrupts on ADC0 (S32K118)

[Arunpk]

Hi,

I’m currently using the S32K118 MCU in my project for ADC-based signal detection. I’m facing an issue when configuring multiple ADC channels on the same ADC instance (ADC0) with range compare functionality.

Problem Description:
I need to monitor multiple channels simultaneously on ADC0.

Range compare is configured on each channel to generate an interrupt when the ADC value is within a defined threshold.

However, I’ve observed that only the last configured channel triggers the interrupt, and the others are ignored.

There is only one ISR available for ADC0, and I couldn’t find any API or method to identify which channel triggered the interrupt.

Application Requirement:
I need to monitor two ADC channels (more than 6 values in each) continuously.

Each channel is configured with a range, and I need an interrupt whenever any configured channel value falls within its respective threshold.

Both channels should be active concurrently and trigger ISR independently.

Request:
Is there a recommended way to configure multiple channels with range compare on the same ADC instance (ADC0) so that all can trigger interrupts as needed?

How can I identify the source channel inside the ADC ISR?

If this approach is not supported on ADC0, would ADC1 (if available on S32K118) be a viable workaround?

Please advise how this can be resolved or provide guidance or examples if available.

Thanks in advance for your support.

[PetrS]

Hi,

not sure how do you perform multiple conversion which code/driver youa re using. But the interrupt should be triggered for each converted channel if compare condition is true and channel interrupt is enabled.

Compare functionality is same and valid for all channels. After any input is sampled and converted, if the condition selected evaluates true, respective SC1n[COCO] is set and result can be read from respective Rn. If the compare condition is not true, SC1n[COCO] is not set and the conversion result data will not be transferred to the result register, Rn.
An ADC interrupt is generated when SC1n[COCO] is set and the respective ADC interrupt is enabled, that is, SC1n[AIEN] = 1.
Withing ADC interrupt you can read SC1n[COCO] to know which channel triggers interrupt, then read Rn to clear COCO.

BR, Petr