/****************************************************************************************************/
void DmaInit(void)
{
uint8_t index = 0;
DmaMuxInit();
SIM->PLATCGC |= SIM_PLATCGC_CGCDMA(1);
DMA->TCD[0].CSR &= 0xFFFFFFFF ^ DMA_TCD_CSR_DONE_MASK;
DMA->TCD[0].SADDR = DMA_TCD_SADDR_SADDR(&(FTM0->CONTROLS[1].CnV));
DMA->TCD[0].SOFF = DMA_TCD_SOFF_SOFF(0);
DMA->TCD[0].ATTR = DMA_TCD_ATTR_SMOD(0) | DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_DMOD(0) | DMA_TCD_ATTR_DSIZE(1);
DMA->TCD[0].NBYTES.MLOFFNO = DMA_TCD_NBYTES_MLNO_NBYTES(2);
DMA->TCD[0].SLAST = 0;
DMA->TCD[0].DADDR = DMA_TCD_DADDR_DADDR(&(RxDmaCan1DataFifo[0]));
DMA->TCD[0].DOFF = DMA_TCD_DOFF_DOFF(0);
DMA->TCD[0].CITER.ELINKNO = DMA_TCD_CITER_ELINKNO_CITER(1) | DMA_TCD_CITER_ELINKNO_ELINK(0);
DMA->TCD[0].DLASTSGA = DMA_TCD_DLASTSGA_DLASTSGA(0);
DMA->TCD[0].BITER.ELINKNO = DMA_TCD_BITER_ELINKNO_BITER(1) | DMA_TCD_BITER_ELINKNO_ELINK(0);
#ifndef DMA_CHANNEL_IQR
DMA->TCD[0].CSR = DMA_TCD_CSR_BWC(0) | DMA_TCD_CSR_MAJORELINK(0) | DMA_TCD_CSR_MAJORLINKCH(0) | DMA_TCD_CSR_ESG(0) | DMA_TCD_CSR_DREQ(0) | DMA_TCD_CSR_INTHALF(0) | DMA_TCD_CSR_INTMAJOR(1) | DMA_TCD_CSR_START(0);
#else
DMA->TCD[0].CSR = DMA_TCD_CSR_BWC(0) | DMA_TCD_CSR_MAJORELINK(0) | DMA_TCD_CSR_MAJORLINKCH(0) | DMA_TCD_CSR_ESG(0) | DMA_TCD_CSR_DREQ(0) | DMA_TCD_CSR_INTHALF(0) | DMA_TCD_CSR_INTMAJOR(0) | DMA_TCD_CSR_START(0);
#endif
DMA->SERQ = DMA_SERQ_SERQ(0);
#ifndef DMA_CHANNEL_IQR
INT_SYS_EnableIRQ(DMA0_IRQn);
#endif
}
/****************************************************************************************************/
static void DmaMuxInit (void)
{
PCC->PCCn[PCC_DMAMUX_INDEX] |= PCC_PCCn_CGC_MASK;
DMAMUX->CHCFG[0] &= ~DMAMUX_CHCFG_ENBL(1);
DMAMUX->CHCFG[0] |= DMAMUX_CHCFG_SOURCE(36);
DMAMUX->CHCFG[0] |= DMAMUX_CHCFG_ENBL(1);
}
/****************************************************************************************************/
void FTM0_init(void)
{
PCC->PCCn[PCC_FTM0_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Ensure clk disabled for config */
PCC->PCCn[PCC_FTM0_INDEX] |= PCC_PCCn_PCS(1) | PCC_PCCn_CGC_MASK; /* Clock Src=1, 8 MHz SOSCDIV1_CLK */
/* Enable clock for FTM regs */
FTM0->MODE |= FTM_MODE_WPDIS_MASK; /* Write protect to registers disabled (default) */
FTM0->SC = 0x000C0107;
/* Enable PWM channel 0 input*/
/* Enable PWM channel 1 input*/
/* Enable PWM channel 2 output*/
/* Enable PWM channel 3 output*/
/* TOIE (Timer Overflow Interrupt Ena) = 1 (enable) */
/* CPWMS (Center aligned PWM Select) = 0 (default, up count) */
/* CLKS (Clock source) = 0 (default, no clock; FTM disabled) */
/* PS (Prescaler factor) = 7. Prescaler = 128 */
FTM0->COMBINE = 0x00000004;/* FTM mode settings used: DECAPENx = 1, DECAP = 0£¬MCOMBINEx = 0, COMBINEx=0 */
FTM0->POL = 0x00000000; /* Polarity for all channels is active high (default) */
FTM0->MOD = 62500 - 1 ; /* FTM1 counter final value (used for PWM mode) */
/* FTM1 Period = MOD-CNTIN+0x0001 ~= 62500 ctr clks */
/* 8MHz /128 = 62.5kHz -> ticks -> 1Hz */
}
/****************************************************************************************************/
void FTM0_CH0_IC_init(void)
{
FTM0->CONTROLS[0].CnSC = 0x00000059; /* FTM0 ch6: Input Capture fall edge */
/* CHIE (Chan Interrupt Ena) = 1 (enable) */
/* MSB:MSA (chan Mode Select)=0b01, Continue */
/* ELSB:ELSA (ch Edge/Level Select)=0b10, fall*/
/* DMA enable */
}
/****************************************************************************************************/
void FTM0_CH1_IC_init(void)
{
FTM0->CONTROLS[1].CnSC = 0x00000045; /* FTM0 ch7: Input Capture rising edge */
/* CHIE (Chan Interrupt Ena) = 1 (enable) */
/* MSB:MSA (chan Mode Select)=0b00, Continue */
/* ELSB:ELSA (ch Edge/Level Select)=0b01, rise*/
/* DMA enable */
}