How to prevent flash accesses during RWSC flash wait state update (S32K344)?

[andye]

The documentation for flash wait states on the S32K344 (configured by CTL.RWSC) says:

Updates to this configuration field that control reads must take place only when the flash memory is idle. Changing configuration settings while flash memory access is in progress can lead to non-deterministic behavior.

I assume this means code to change RWSC ought to execute from RAM or TCM, instead of from flash.

However, due to pipelining and prefetching in the Cortex-M7 core, it seems to me that flash accesses could still occur in the background even if the instructions to change RWSC execute from RAM or TCM. This makes me worried about triggering this non-determinism even with the wait state change code executing from outside flash.

Could you please clarify what the safe RWSC update procedure is on the S32K344, which avoids any non-determinism? Is just executing the RWSC change code from RAM or TCM sufficient?

[davidtosenovjan · Accepted solution]

You would apparently need to flush the pipeline (instructions ISB/DSB) before start of execution from RAM accessing flash control register.

[andye]

Hello, thank you for the reply! I was curious if NXP recommends anything else be done, such as disable the I-cache, or configure the MPU to mark flash as XN/non-readable to inhibit speculative accesses during the wait state change. But I actually now see in section 5.2 a similar recommendation for avoiding flash accesses during flash operations, which seems like it also applies here. I think this is sufficient for me, thank you for the help.