Hi support team,
We're using UART Tx FIFO function with CTS feature enabled. After having checked with the errata file of S32K146, we find that the ERR051629 is related to our case. My understanding of this issue is that if the CTS pin is changed to low during the tx FIFO is flushing with CTS feature enabled, the transmit complete bit will not be set, the workaround is to clear the MODIR[TXCTSE] bit before setting FIFO[TXFLUSH] bit to 1 if the CTS feature is enabled, and then set the MODIR[TXCTSE] bit again, such as the following code changes based on the NXP RTD code:
/**
* @brief : Flush Tx Buffer
*
* This function causes all data that is stored in the transmit FIFO/buffer to be flushed.
* *
* @Param Base LPUART Base pointer
*/
static inline void Lpuart_Uart_Ip_FlushTxBuffer(LPUART_Type * Base)
{
Base->MODIR &= 0xFFFFFFFEu; /*Clear (MODIR[TXCTSE]) bit*/
Base->FIFO |= 0x00008000u; /*reset the transmit FIFO (FIFO[TXFLUSH] = 0b1)*/
Base->MODIR |= 0x00000001u; /*Set (MODIR[TXCTSE]) bit*/
}
Is my understanding correct? If it's not correct, how should I handle this problem?
