I created a project on S32K324 and a hardfault occurs during clock initialization.
I am using RTD4.0.0, D2403 and FreeRtos V10.6.0.
A hardfault occurs when loading the critical section reentry_guard_MCU_EXCLUSIVE_AREA_01. It seems to be a RAM access issue.
What should I check?
Below are the problematic parts.
Hi @jwkang
In the Integration Manual for S32K3_S32M27X MCU Driver it is noted that MCU_EXCLUSIVE_AREA_01 is used in functions Clock_Ip_InitClock() and Clock_Ip_DisableClockMonitor() to protect against itself in the context of multicore usage of it and ISR event.
For example a critical situation will be: Clock_Ip_InitClock() is called from Core0 and during the excecution in Core0, Clock_Ip_InitClock() is called from another core (Core1). It is called from Core1 while the first call is still in progress (it has not returned yet).
BR, VaneB
Yes, I understand the content. When I looked at the address, it seemed to be a memory access problem, so I modified the memory map in the linker file. Then, a hardfault occurs in OsIf_Init.
Looking at the map file, the address is in the mcal_bss area.
Is the address in my linker file wrong?
Please, check this.
Thanks.
Hi @jwkang
Let's first try to work with access to MCU_EXCLUSIVE_AREA_01. Return the linker file to how it was before the OsIf_Init function failed and if possible could you give me more details regarding how you are using the Clock_Ip_Init() function.
This problem was caused by a problem with the generated Linker file.
In the linker_flash_c0_s32k324.ld file, as shown in the figure, the hardfault stopped occurring when the __RAM_CACHEABLE_SIZE value was changed to 0x12.
It seems that there is a problem with the project creation.
Can you tell me what the __RAM_SHAREABLE_SIZE, __RAM_NO_CACHEABLE_SIZE, and __RAM_CACHEABLE_SIZE values mean?
Please check if the values are correct.