Dear Qian,
all six GD3162 devices share the same MOSI / MISO / SCLK / CSB. The devices are connected in series, forming one long shift register. Each GD3162 requires a 24‑bit frame. Please refer to the section 12. in the GD3162 full datasheet for the SPI interface description.
Please download the full GD3162 datasheet from the GD3162 product page, under the Secure section.
In the Figure 43. is shown SPI timing, from which required SPI mode can be deduced.
| SPI mode | Clock polarity (CPOL) |
Clock phase (CPHA) |
Data is shifted out on | Data is sampled on |
|---|---|---|---|---|
| 0 | 0 | 0 | falling SCLK, and when SS activates | rising SCLK |
| 1 | 0 | 1 | rising SCLK | falling SCLK |
| 2 | 1 | 0 | rising SCLK, and when SS activates | falling SCLK |
| 3 | 1 | 1 | falling SCLK | rising SCLK |
Figure 47. shows Daisy chain data transmission.
In the Table 34. are listed SPI registers.
Do I need to configure registers first?
[A] Yes. All GD3162 devices must receive their configuration via SPI before entering normal PWM operation.
If some devices need different settings, write to all first, then overwrite the ones that differ. Add 100us delay after each register write.
With Best Regards,
Jozef
