GD3162 CONFIG_EN PIN

[21221sad]

Hello NXP Team,

I’m working with your official GD3162 driver code and facing an abnormal issue with the MODE2 register write operation, and would appreciate your help to resolve it.

Here are the full details of the operation and phenomenon:

1. Read the MODE2 register: returned 0x0660D4, meaning CONFIG_EN = 0x0 (red box)
2. Write 0x86646F to the MODE2 register (yellow box)
3. Read back the MODE2 register after writing: returned 0x8660D3, with the CONFIG_EN bit still at 0x0

Could you please help explain why the CONFIG_EN bit cannot be set successfully, and advise on the correct procedure to configure this register?

Thank you.

[TomasVaverka · Accepted solution]

Hello Wentao,

Please try following:

Both LV and HV domains powered and stable. If LV comes up before HV, the device may flag WDOG_FLT until HV powers; clear it before proceeding. Otherwise, configuration writes can be blocked or immediately reset by the fault state. Clear watchdog (and any other) latched faults by writing ‘1’ to the corresponding STATUSx bit once both domains are valid.

INTB not asserting an uncleared fault. If INTB is low due to a latched fault, clear it first as above; the official sequence from NXP support explicitly shows clearing faults and then entering configuration.

Step 1: Set CONFIG_EN=1 in MODE2 → “PWM operation will be disabled, INTB stays high.”

Step 2: (optional) If you plan to reset, set RESET=1 (still in MODE2) → “INTB goes low and registers reset to defaults; PWM disabled.”

Step 3: Clear RESET back to 0 → “INTB returns high; now you can write configuration registers.”

Stay in config (i.e., keep CONFIG_EN=1) until all config registers are written; then write CONFIG_EN=0 to exit.

Write MODE2 (CONFIG_EN=1), send a read of MODE2, discard first read, take second read as valid value.

BRs, Tomas

[21221sad]

Thanks a lot! It works perfectly.