Hi,
I'm trying to make use of FlexIO module on S32K358. My application is not a standard communication protocal, so the components in RTD driver cannot help me out. I have to write the registers directly.
Specifically, I am using 3pins, 1 shifter and 1 timer in FlexIO. Ideally, trigger signal rising edge on pin1 triggers the timer, and then timer outputs clk signal on pin2 to acquire data, at the same time generates the shift clock for the shifter. Shifter read the data from pin0. Eventually, the data frame is read from shifterbuf, when eMIOS interrupt is triggered by trigger signal falling edge. The pin configuration is as followed.
The question is, I cannot even see the FlexIO output clk signal on pin2 on the oscilloscope. I am pretty sure the the clock and pin initialazation is correct, and trigger signal exists, because it also tirggers eMIOS interrupt and that works fine. What might go wrong? The FlexIO configuration is as followed.
#include "S32K358_FLEXIO.h"
Clock_Ip_Init(&Clock_Ip_aClockConfig[0]);
Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals, g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals);
IP_FLEXIO->CTRL = (uint32)1u; //enable FlexIO
IP_FLEXIO->SHIFTCFG[0] = FLEXIO_SHIFTCFG_PWIDTH(0) | //1 bit shift
FLEXIO_SHIFTCFG_SSIZE(0) | //32bit shift register
FLEXIO_SHIFTCFG_LATST(0) | //store the pre-shift register state
FLEXIO_SHIFTCFG_INSRC(0) |//pin input
FLEXIO_SHIFTCFG_SSTOP(0) |//disable stop bit
FLEXIO_SHIFTCFG_SSTART(0); //disable start bit
IP_FLEXIO->SHIFTCTL[0] = FLEXIO_SHIFTCTL_TIMSEL(0) | //timer0 generate the shift clock
FLEXIO_SHIFTCTL_TIMPOL(1) | //shift occurs on the negative edge
FLEXIO_SHIFTCTL_PINCFG(0) | //shifter pin output disabled
FLEXIO_SHIFTCTL_PINSEL(0) | //select FXIO_D0 as shifter input.
FLEXIO_SHIFTCTL_PINPOL(0) | //shifter pin active high
FLEXIO_SHIFTCTL_SMOD(1); //receive mode
IP_FLEXIO->TIMCMP[0] = 0x00007951; //8 bit baud rate mode
// 16 bit for 1 data frame, 5MHz baudrate (160MHz for FlexIO_clk)
//TIMCMP[7:0]=15 baudrate divider/2 - 1
//TIMCMP[15:8]=31 bits*2-1
IP_FLEXIO->TIMCFG[0] = FLEXIO_TIMCFG_TIMOUT(3) | //Logic zero when enabled and on timer reset
FLEXIO_TIMCFG_TIMDEC(0) | //Decrement counter on FLEXIO clock; shift clock equals timer output
FLEXIO_TIMCFG_TIMRST(6) | //Timer reset on trigger rising edge
FLEXIO_TIMCFG_TIMDIS(6) | //Timer disabled on trigger falling edge
FLEXIO_TIMCFG_TIMENA(6) |//Timer enabled on trigger rising edge
FLEXIO_TIMCFG_TSTOP(0) | //disable stop bit
FLEXIO_TIMCFG_TSTART(0); //disable start bit
IP_FLEXIO->TIMCTL[0] = FLEXIO_TIMCTL_TRGSEL(2) | //select FXIO_D1 as internal trigger
FLEXIO_TIMCTL_TRGPOL(0) | //trigger active high
FLEXIO_TIMCTL_TRGSRC(1) | //internal trigger
FLEXIO_TIMCTL_PINCFG(3) | //timer pin output
FLEXIO_TIMCTL_PINSEL(2) | //select FXIO_D2 as timer pin
FLEXIO_TIMCTL_PINPOL(0) | //timer pin active high
FLEXIO_TIMCTL_PININS(0) | //PINSEL selects pin input and output
FLEXIO_TIMCTL_ONETIM(0) | //Generate the timer enable event as normal
FLEXIO_TIMCTL_TIMOD(1); //8-bit baud counter mode
Thanks
