Fault Injection of ECC error on RAM

[Bhumika_NL]

I need to inject ECC errors on Different types of RAM on real Hardware.
Also I need to read them on all available types of RAM.
I Need a exact way on how to do this .

Also i am using S32K3GHS Micro-controller .
please provide some kind of document or some methodology on how to do this.

[danielmartynek]

Hello @Bhumika_NL,

NXP provides Safety Peripheral Drivers (SPD) for the S32K3xx family.
The eMCEM driver controls the EIM module, which is used to inject ECC errors.
The SPD drivers are available free of charge as part of the S32K3xx Standard Software Package:

https://www.nxp.com/webapp/swlicensing/sso/downloadSoftware.sp?catid=SW32K3-STDSW-D

NXP also offers the Safety Software Framework (SAF) as a paid premium solution, which includes SPD as part of its package. 

The full SAF version is now also available for evaluation and development purposes only under NDA free of charge.
If you are interested, please contact your assigned NXP FAE (if your company has one) or reach out through your local NXP distributors.

https://www.nxp.com/design/design-center/software/functional-safety-software/s32-safety-software-fra...

BR, Daniel

[Bhumika_NL]

I want to inject the ECC error on RAM using our own function and a pseudocode or samplecode for reference.

Also Could you mention more details on how to inject fault without using any module or drivers . or let me know if it is a feasible way to do that.

[danielmartynek]

Hi @Bhumika_NL,

Have a look at this example:
https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-EIM-ERM-DTCM-SRAM-Baremetal-v3-0-S3...

Regards,

Daniel

[Bhumika_NL]

Hello Daniel ,
Thank you so much for your response
Apologies for not checking this response .

I checked your example , I was more expecting like a kind of pseudocode which I could use it to develop my own function for detecting ECC errors

[danielmartynek]

Hi @Bhumika_NL,

Unfortunately, we don't have such pseudo code.

BR, Daniel

[Bhumika_NL]

Hello danielmartynek ,

I found out one of the module in reference manual where it is mentioned like we could inject ECC errors on different types of memories .

45.2
Overview
The Error Injection Module (EIM) is mainly used for diagnostic purposes. It provides a method to test the diagnostics (memory ECC, interconnect parity) by error injection in the field. See the chip-specific EIM information to determine which functional safety features are supported by this method.
EIM enables you to inject artificial errors on error-checking mechanisms of a system, such as ECC for RAM read data and parity bits. For each such mechanism that EIM supports on the chip, EIM can inject single-bit and multi-bit inversions on data in the applicable target bus. Injecting faults on memory accesses can be used to exercise the SEC-DED ECC function of the related system.
45.2.1
Features
The EIM includes these features:
•
Supports 19 error injection channels. See the chip-specific EIM information for channel assignment details.
•
Protection against accidental enable and reconfiguration error injection function via two-stage enable mechanism

I need some more information on which channel we could inject error and how using EIM module


Also in the ERM module i saw in reference manual of s32k3 like there are different memories like memory 1 , memory 1 and so on ..

But it is nowhere mentioned which memory is memory0 , which memory is memory 1 and like so on ..

Could you also give me some information on these .

ENCIE0
ENCIE0
Enable Memory 0 Non-Correctable Interrupt Notification
This field is not supported in every instance. The following table includes only supported registers.
NOTE
Instance
Field supported in
Field not supported in
ERM_0
CR0
—
ERM_1
—
CR0
0b - Interrupt notification of Memory 0 non-correctable error events is disabled.
1b - Interrupt notification of Memory 0 non-correctable error events is enabled.
29-28
—
Reserved
27
ESCIE1
ESCIE1
Enable Memory 1 Single Correction Interrupt Notification
This field is not supported in every instance. The following table includes only supported registers.
NOTE
Instance
Field supported in
Field not supported in
ERM_0
CR0
—
ERM_1
—
CR0
0b - Interrupt notification of Memory 1 single-bit correction events is disabled.

[danielmartynek]

Hi @Bhumika_NL,

You can find the complete EIM channel assignment directly in the Reference Manual, Revision 12:

Table 273 – EIM channel mapping – S32K3x1, S32K3x2, S32K344/S32K324/S32K314

For the ERM module, the memory‑to‑channel mapping is provided in:

Table 291 – ERM_0 channel mapping for all devices except S32K389

Regards,

Daniel

[Bhumika_NL]

I am feeling it quite difficult to find out reference manual which is of revision 12 .
But right now I am using revision 4 , in that I could not find any info related to channel assignment to memories in Table 273 and Table 291 . I could see some other information there .

Could you please suggest us something here in this case

[danielmartynek]

Here is the latest manual (rev. 12):

https://www.nxp.com/webapp/Download?colCode=S32K3XXRM

BR, Daniel

[Bhumika_NL]

Thank you so much , I will check this manual once then

[Bhumika_NL]

We are currently working on the NXP S32K394 microcontroller, and we have confirmed this as our target device.

However, the reference manual we were using earlier does not cover this specific controller. Therefore, could you please share the appropriate Reference Manual for the S32K394 series, specifically including details on:

• Channel assignment for different memory regions
• Mapping related to the EIM (Error Injection Module)
• Mapping related to the ERM (Error Reporting Module)

This information will help us proceed with validation and testing using the debugger.

[danielmartynek]

Thank you, I did not know you use S32K394.

In the S32K39, S32K37 and S32K36 Reference Manual, Rev. 4, 11/2024

Table 210. ACP_EIM_0

Table 211. ACP_EIM_1

Table 212. ACP_EIM_2

Table 219. ACP_ERM_0 channel mapping

Table 220. ACP_ERM_1 channel mapping

Regards,

Daniel

[Bhumika_NL]

I used the above register of EIM module and i am able to successfully inject the ECC errors on s32k3(both single and multibit )  for SRAM0 memory location .
 but for other memory locations , i am unable to inject the ECC errors in the same way .

Attaching the code for reference 

typedef enum

{

    EIM_MEM_SRAM_L = 0,

    EIM_MEM_SRAM_U = 1

} EIM_MemoryType;

typedef enum

{

    EIM_ERROR_SINGLE_BIT = 1,

    EIM_ERROR_DOUBLE_BIT = 2

} EIM_ErrorType;

#define IP_EIM_0_BASE  0x4050C000

#define IP_EIM_1_BASE 0x40510000

#define IP_EIM_2_BASE 0x40514000

#define EIMCR_BASE_ADDR       (IP_EIM_2_BASE + 0x0 )

#define EICHEN_BASE_ADDR       (IP_EIM_2_BASE + 0x4)

#define EICHD0_WORD0_ADDR     (IP_EIM_2_BASE + 0x100)

#define EICHD0_WORD1_ADDR     (IP_EIM_2_BASE + 0x104)

void EIM_InjectSramEccError(EIM_MemoryType mem, EIM_ErrorType errType, volatile uint32 *testAddr)

{

    uint8 channel = (uint8)mem;

*(volatile uint32 *) EICHEN_BASE_ADDR =0x80000000;

*(volatile uint32 *) EIMCR_BASE_ADDR =0x00000001;

//(void)*(volatile uint32 *) EIMCR_BASE_ADDR;

    /* Step 1: Clear previous configuration */

  *(volatile uint32 *)EICHD0_WORD0_ADDR = 0x00000000;

  *(volatile uint32 *)EICHD0_WORD1_ADDR =  0x00000000;

    /* Step 2: Configure ECC injection */

    if (errType == EIM_ERROR_SINGLE_BIT)

    {

        /* Flip 1 data bit → correctable */

        *(volatile uint32 *)EICHD0_WORD1_ADDR = 0x00000001;

    }

    else

    {

        /* Flip 2 data bits → uncorrectable error */

       *(volatile uint32 *)EICHD0_WORD1_ADDR = 0x00000003;

    }

    /* Step 3: Dummy write (ensure valid ECC exists) */

    *testAddr = 0xA5A5A5A5;

    /* Step 4: Read back → triggers ECC error */

    volatile uint32 readVal = *testAddr;

    (void)readVal; /* جلوگیری optimization */

   *(volatile uint32 *) EICHEN_BASE_ADDR =0x80000000;

}

void test_ecc()

{

    volatile uint32 *addr = (uint32 *)0x20400000; // Example SRAM_L address

    /* Test single-bit error (correctable) */

    EIM_InjectSramEccError(EIM_MEM_SRAM_L, EIM_ERROR_SINGLE_BIT, addr);

    /* Test double-bit error (uncorrectable) */

    EIM_InjectSramEccError(EIM_MEM_SRAM_L, EIM_ERROR_DOUBLE_BIT, addr);

}


could you please correct me if something is wrong here in procedure or understanding 
if anything more needs to be added then also please let me know .

But for SRAM0 , i am able to inject fault for ECC and observe in ERM register that the fault is set.

Thanks in Advance !

[danielmartynek]

Hi @Bhumika_NL,

Can you create a new thread?

This one has mane QA already.

Thank you,

BR, Daniel

[Bhumika_NL]

Hello @danielmartynek ,

can you please help us on this ?