I want to Provide FPU enablement and support on NXPS32K38. So, I want to detect the exceptions of IOC and DZC and raise an Interrupt accordingly whenever the system notices a DZC or IOC and perform exception handling. I want to retrieve the data using which these exceptions are getting raised. Like if there is an 5/0 operation and the ISR is raised I want to retrieve these values 5 and 0 in ISR and use these to do the exception handling mechanism. As per the datasheet/Reference Manual, the info regarding these were captured using the FPCCR extended stack frame and the FPU S0-S31 registers capture the information. But while I am trying to access the registers, I am getting the same values all the time even after I try to change the exception raising mechanism. So, does it mean the S0-S31 registers doesn't contain the information of such exceptions? If yes, where can I get this control data from?
Do you have set following register properly? Also statuses are reported in core's FPSCR register.
Yes, we have set the register properly. And all the statuses are recorded in the FPSCR.
Also what you are describing sounds me as lazy stacking feature, described in ARM documents:
Also there is an appnote for that:
https://developer.arm.com/documentation/dai0298/a