FLash driver implementation for write operation in S32K311

emb-enockal · ‎11-12-2025

Hi,

I'm facing issue in writing data to PFlash, I have followed as per reference manual, but still I'm not able to write to memory. Kindly help me with this. Since its time critical.

Also I'm attaching my code for your reference.

Thank you,

danielmartynek · ‎11-12-2025

Hi @emb-enockal,

Can you elaborate on the description of the issues?

Do you see any error flags?

I recommend starting with a blocking method for simplicity:

The DATA registers must be aligned to the quad-page.

You cannot execute code from the block that is being programmed.

Regards,

Daniel

Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. 
NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

emb-enockal · ‎11-13-2025

Hi everyone,

I’m stuck on PFlash/DFlash programming for S32K311 (48-pin). I can now program P-Flash when I place a breakpoint at the end of the write function, but if I don’t keep that breakpoint the CPU jumps to disassembly and RWE flag is set to 1.

Also I cannot unlock D-Flash (all unlock attempts appear to be ignored). Please advise.

what I observed is:

PFlash write sequence completes only when I keep a breakpoint in the write function. If I remove that breakpoint the CPU goes to disassembly immediately after the write request (looks like an interrupt/fetch fault).
D-Flash remains locked despite writing the following unlock sequences:
PFLASH.PFCBLKU_SPELOCK[0].R = 0x00000000U; /* clear UTEST block lock (tried) */
/* clear module locks */
FLASH.SPELOCK.R = 0x00000000U;
FLASH.SSPELOCK.R = 0x00000000U;
/* platform-level block unlock */
PFLASH.PFCBLK_SPELOCK[0].R = 0x00000000U;
PFLASH.PFCBLK_SSPELOCK[0].R = 0x00000000U;
Also attached code for your reference.

danielmartynek · ‎11-13-2025

Hi @emb-enockal,

The flash programming code must not reside in the same flash block that is being programmed.

If you need to program the same flash block, ensure the execution code is placed in SRAM.

In this example, the C40_Ip APIs are located in SRAM:
For reference, see: https://community.nxp.com/t5/S32K-Knowledge-Base/S32K312-C40-Ip-SRAM-RTD-500-DS35/ta-p/2074245.

DFlash is located in Block_2, locked by SPELOCK[2] and SSPELOCK[2].

Regards,

Daniel

emb-enockal · ‎11-14-2025

Hi Daniel,

Thank you for the clarification.

Yes, I realized that I was trying to execute the write function from the same PFlash block that I was programming. After moving the write routine to another block, it started working.

However, I have two follow-up issues:

PFlash consecutive writes
When I write 8 bytes at address 0x00480000, it succeeds.
But if I try to write the next 8 bytes at 0x00480008, the operation fails.
The next address where a write is successful is 128 bytes later.
It looks like the controller only allows programming at 128-byte (quad-page) boundaries.
Is there any way to program smaller chunks (8 bytes) consecutively within the same quad-page, or must all 128 bytes be written at once?
DFlash unlock issue
As recommended, I tried unlocking Block_2 using SPELOCK[2] and SSPELOCK[2], but the block remains locked.
I also attempted clearing the module-level and platform-level lock registers, but the DFlash region still does not unlock.
Below is the unlock sequence I attempted:
PFLASH.PFCBLK_SSPELOCK[0].R = 0x00000000U; //PFlash Block0
PFLASH.PFCBLK_SSPELOCK[1].R = 0x00000000U; //PFlash Block1
FLASH.SPELOCK.R = 0x00000000U;
FLASH.SSPELOCK.R = 0x00000000U;
FLASH.XSPELOCK.R = 0x00000000u;
FLASH.XSSPELOCK.R = 0x00000000u;

Could you please help me understand the correct way to unlock DFlash Block_2 and confirm whether consecutive writes inside the same quad-page are supported?
Thank you for your assistance.

emb-enockal · ‎11-18-2025

Hi Daniel,

1. I attempted unlocking using all register combinations mentioned in the Reference Manual, including:

PFLASH.PFCBLK_SSPELOCK[0].R = 0x00000000U; //PFlash Block0

PFLASH.PFCBLK_SSPELOCK[1].R = 0x00000000U; //PFlash Block1

FLASH.SPELOCK.R = 0x00000000U;

FLASH.SSPELOCK.R = 0x00000000U;

FLASH.XSPELOCK.R = 0x00000000u;

FLASH.XSSPELOCK.R = 0x00000000u;

PFLASH.PFCBLK_SPELOCK[0].R = 0x00000000U;

PFLASH.PFCBLK_SPELOCK[1].R = 0x00000000U;

PFLASH.PFCBLK_SPELOCK[2].R = 0x00000000U;

PFLASH.PFCBLKU_SPELOCK[0].R = 0x00000000U; // UTEST block lock

However, DFlash always remains locked, and any erase/program attempt sets PES=1 .

Could you please clarify:

The correct register and register index for D-Flash block on S32K311.

Whether D-Flash on S32K311 requires a special unlock mechanism (UTEST fuse, FCCU, life-cycle state, etc.).

Any reference example showing successful D-Flash unlock + write.

2. Unable to unlock last 256 KB of P-Flash:

Anything at or above 0x004B0000 – 0x004FFFFF remains locked even after using all register combinations mentioned above.

Is this region controlled by a different lock block (Block 2?) or shared with D-Flash?

danielmartynek · ‎11-19-2025

HI @emb-enockal,

1.

Unlock just the first sector in DFLASH at 0x1000_0000:

IP_PFLASH->PFCBLK_SPELOCK[2] &= ~(1U << 0);

Can you test it?

Regards,

Daniel

Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. 
NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

emb-enockal · ‎11-21-2025

Hi Daniel,

Thank you — D-Flash is now working after using:

IP_PFLASH->PFCBLK_SPELOCK[2] &= ~(1U << 0);

However, I still have one remaining issue:

Unable to unlock the last 256 KB of P-Flash (0x004B0000 – 0x004FFFFF)

Everything below 0x004B0000 is working correctly.
But any write/erase attempt in the region:

0x004B0000 – 0x004FFFFF

fails with PES = 1, exactly like a locked block.

I tried clearing all P-Flash lock registers:

PFLASH.PFCBLK_SSPELOCK[0].R &= ~(1U <<0); //PFlash Block0

PFLASH.PFCBLK_SSPELOCK[1].R &= ~(1U <<0); //PFlash Block1

FLASH.SPELOCK.R &= ~(1U <<0);

FLASH.SSPELOCK.R &= ~(1U <<0);

FLASH.XSPELOCK.R &= ~(1U <<0);

FLASH.XSSPELOCK.R &= ~(1U <<0);

PFLASH.PFCBLK_SPELOCK[0].R &= ~(1U <<0);

PFLASH.PFCBLK_SPELOCK[1].R &= ~(1U <<0);

PFLASH.PFCBLK_SPELOCK[2].R &= ~(1U <<0);

PFLASH.PFCBLKU_SPELOCK[0].R &= ~(1U <<0); // UTEST block lock

But this upper P-Flash area remains locked, even though D-Flash unlock and write are now working.

Any clarification on the correct way to unlock and program the upper 256 KB P-Flash region would be very helpful.

Thanks again for your support.

danielmartynek · ‎11-21-2025

Hi @emb-enockal,

I can unlock the supersector at 0x4B0000

IP_PFLASH->PFCBLK_SSPELOCK[1] &= ~(1U << 3);

And reprogram it:

Refer to these tables in the RM:

Table 197. Configuration details when the HSE firmware usage feature flag is disabled

Table 199. Configuration details when the HSE_B firmware usage feature flag is enabled

Table 200. AB swap configuration

Regards,

Daniel

danielmartynek · ‎11-14-2025

Hi @emb-enockal,

To program 8 bytes starting at 0x00480008, you need to write the data in DATA[2-3] registers.

Regarding the lock, I'm out of office until Tuesday, I cannot test it on HW right now.

I would recommend that you use the RTD drivers (C40_Ip) for reference.

Regards,

Daniel