Hello, the MCU uses S32K144 and operates with 5V power supply. Currently configuring CAN communication, CAN0 and CAN2 are enabled.
CAN0 is high-speed CAN (TJA1050) at 500K, CAN2 is low-speed CAN (TJA1055T/3). CAN0 is configured at 500K without issues, CAN0->CTRL1 = 0x00DB0006 is 500K.
Now I want to configure CAN2 at 100K, CAN2->CTRL1 = 0x00CF0033, but other CAN devices cannot receive data.
If the CAN bitrate is set to 100K, what should CAN2->CTRL1 be?
Or is it feasible to set TJA1050 to 100K? I also tried setting CAN0 to 100K but it was unsuccessful.
void FLEXCAN2_init(void)
{
#define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */
uint32_t i=0;
PCC->PCCn[PCC_FlexCAN2_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN2 */
CAN2->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */
CAN2->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKsrc=0: Clock Source = oscillator (8 MHz) */
CAN2->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/
while (!((CAN2->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT))
{
/*code*/
}
/* Good practice: wait for FRZACK=1 on freeze mode entry/exit */
CAN2->CTRL1 = 0x00CF0033; /* 0x00DB0006 Configure for 500 KHz bit time 0x00DF000F 125Kbps */
/* Time quanta freq = 16 time quanta x 500 KHz bit time= 8MHz */
/* PRESDIV+1 = Fclksrc/Ftq = 8 MHz/8 MHz = 1 */
/* so PRESDIV = 0 */
/* PSEG2 = Phase_Seg2 - 1 = 4 - 1 = 3 */
/* PSEG1 = PSEG2 = 3 */
/* PROPSEG= Prop_Seg - 1 = 7 - 1 = 6 */
/* RJW: since Phase_Seg2 >=4, RJW+1=4 so RJW=3. */
/* SMP = 1: use 3 bits per CAN sample */
/* CLKsrc=0 (unchanged): Fcanclk= Fosc= 8 MHz */
for(i=0; i<64; i++ ) /* CAN2: clear 16 msg bufs x 4 words/msg buf = 64 words*/
{
CAN2->RAMn[i] = 0; /* Clear msg buf word */
}
for(i=0; i<16; i++ ) /* In FRZ mode, init CAN2 16 msg buf filters */
{
CAN2->RXIMR[i] = 0xFFFFFFFF; /* Check all ID bits for incoming messages */
}
CAN2->RXMGMASK = 0x1FFFFFFF; /* Global acceptance mask: check all ID bits */
CAN2->RAMn[ 4*MSG_BUF_SIZE + 0] = 0x04000000; /* Msg Buf 4, word 0: Enable for reception */
/* EDL,BRS,ESI=0: CANFD not used */
/* CODE=4: MB set to RX inactive */
/* IDE=0: Standard ID */
/* SRR, RTR, TIME STAMP = 0: not applicable */
#ifdef NODE_A /* Node A receives msg with std ID 0x511 */
CAN2->RAMn[ 4*MSG_BUF_SIZE + 1] = 0x14440000; /* Msg Buf 4, word 1: Standard ID = 0x111 */
#else /* Node B to receive msg with std ID 0x555 */
CAN2->RAMn[ 4*MSG_BUF_SIZE + 1] = 0x15540000; /* Msg Buf 4, word 1: Standard ID = 0x555 */
#endif
/* PRIO = 0: CANFD not used */
CAN2->MCR = 0x0000000F; /* Negate FlexCAN2 halt state for 16 MBs */
while ((CAN2->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {}
/* Good practice: wait for FRZACK to clear (not in freeze mode) */
while ((CAN2->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {}
/* Good practice: wait for NOTRDY to clear (module ready) */
}
