Extra SPI Clock Pulse Appears Before CS Line Goes Low on [MCU S32K312]

[Mohmedsohel]

Hello NXP Team,

I’m observing an issue in my SPI communication using the [MCU S32K312] where an

extra SPI clock pulse (SCK) appears before the CS (Chip Select) line goes low.

*Verified SPI config (CPOL/CPHA modes).

My Questions:

1. Why is this extra SCK pulse generated?
2. Is there a workaround or specific configuration to avoid this?
   
   Below I have Attached Project file with that I have attached the snaps taken while testing SPI Communication

[PetrS]

Hi,

CLK low pulse is caused by using first workaround for ERR050456, that is resetting LPSPI module.
If you select 2 workaround, a low pulse would not appear. From RTD300 2nd workaround is properly implemented.
To enable the 2nd workaround, you need to define a macro ERR_IPV_LPSPIV2_0001 and ERR_IPV_LPSPIV2_0001_2ND_SOLUTION

RTD_SPI_UM.pdf:

Anyway, if connected device is enabled by the CS, this SCK extra pulse brings no issue.

BR, Petr

[Mohmedsohel]

Hi PetrS,
Same macros ERR_IPV_LPSPIV2_0001 and ERR_IPV_LPSPIV2_0001_2ND_SOLUTION how can I implement them in MBDT

[Mohmedsohel]

Hi Petrs,
You mean to say that I need to define manually this macro in my project
ERR_IPV_LPSPIV2_0001 and ERR_IPV_LPSPIV2_0001_2ND_SOLUTION

T R
Sohel J

[PetrS]

Hi,

it would be ERR_IPV_LPSPIV2_E050456 and ERR_IPV_LPSPIV2_E050456_2ND_SOLUTION,
defined in Soc_Ips.h

BR, Petr

[Mohmedsohel]

Hi, 

 ERR_IPV_LPSPIV2_E050456 and ERR_IPV_LPSPIV2_E050456_2ND_SOLUTION these same macros how can I define them in MBDT to avoid the incoming extra Clock Pulse

T R
Sohel J

[PetrS]

Hi,

for MBDT please ask on https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/bd-p/mbdt

BR, Petr

[Mohmedsohel]

I just posted the query you said waiting for the response please it is emergency please resolve this asap due to this we struck in technical blocker
T R
Sohel