EMIOS TRGMUX LCU

[amberg]

Hello, 
I'm currently configuring the TRGMUX and LCU0 to route an EMIOS0 channel1 through TRGMUX to LCU0 OUT3 and OUT7. I'm using TRGMUX SEL3 to route EMIOS0 CH1 to LCU0 LC0 INPUT3 so I can use MUXSEL3 = 4.

However, with TRACE32 I see that I need to use MUXSEL0 = 4 to route INPUT3 to LCU0 OUT3. and MUXSEL4 = 4 to route INPUT3 to LCU0 OUT7

But in the datasheet, I see 12 MUXSEL registers—one for each input (1 to 12). so i need to configure MUXSEL3 = 4 and MUXSEL7 = 4 

Could you please explain why this strange behavior occurs

Thank you in advance

[amberg]

It seems that LC0 inputs 0, 1, 2, and 3 all share the same MUXSEL0 register,

LC1 inputs 0, 1, 2, and 3 use the same MUXSEL4,

and LC2 inputs 0, 1, 2, and 3 use the same MUXSEL8.

[_Leo_]

Thank you for your interest in our products and for contributing to our community.

Please refer to the following attached example:

It perform a PWM signal using the emios_0_ch_1_g (PTC1 - yellow signal) in OPWMB mode and using EMIOS_CH_23 in MCB mode as time base. Additionally, such PWM signal is routed through TRGMUX to lcu0_out0 (PTD3 - green signal) and lcu0_out1 (PTD2 - blue signal). Where lcu0_out0 replicates the PWM signal and lcu0_out1 inverts its output to feature complementary signals. Dead-time insertion is implemented with LUT rise/fall filters.

_Leo__0-1756751381567.png

Please use S32DS 3.6, RTD 5.0.0 and S32K31XEVB-Q100.

If you need different SW and/or HW, you can create a new project, do manual config and code copy.

We hope this resolves your issue.

Best regards,
Leonardo