Does SIUL2 VIRT_WRAPPER isolate per‑core access to shared registers?

[luigi_sanpaolo]

Hi,
I am working on S32K324 with two M7 cores, each running its own Design Studio project. Both cores need to control different pins that belong to the same SIUL2 register (same MSCR/GPDO word).

I have read AN14715 and the VIRT_WRAPPER documentation, which explains that SIUL2 can expose multiple virtual interfaces (PDAC) and that XRDC can restrict access per core. However, I cannot find an explicit statement saying whether:

A) VIRT_WRAPPER actually isolates access to the physical SIUL2 registers, preventing two cores from writing to the same register word,
or
B) it does not isolate the physical registers, meaning both cores still write to the same hardware register and therefore require another protection mechanism. Since we have separate designs for each core, what mechanisms do you recommend?

Could you confirm whether the VIRT_WRAPPER does or does not prevent multi‑core write conflicts on the same SIUL2 register?

Thank you.

[Julián_AragónM]

Hi @luigi_sanpaolo,

Virtual Wrapper does isolates the SIUL2 registers by assigning PDACs (Peripheral domain access control) to the respective cores or domain IDs. It locks the XRDC configuration and programs VIRT_WRAPPER registers for pad assignments.

Either HSE-B (which boots first) or main application core should configure PDAC3 to prevent VIRT_WRAPPER being reprogrammed by the second core.

Best regards,
Julián

[luigi_sanpaolo]

Hi,

Thanks for the explanation.

I'd like to clarify a few points to better understand the concurrency scenario. In our use case, we have two cores that may attempt to access the same SIUL2 register at the same time.

Could you provide more details on how concurrent access should be protected?

In particular:

• Is there any built‑in mechanism that prevents race conditions when both cores perform operations on the same register?
• For S32K324 devices, what protection method do you recommend?
• Would using a hardware semaphore be the right approach, or is there another preferred mechanism to coordinate register access between cores?

Any guidance or recommended best practices would be greatly appreciated.

Thanks

[Julián_AragónM]

Hi @luigi_sanpaolo,

SEMA42 must be used in conjunction with XRDC for resource protection, meaning hardware semaphores are used when XRDC, SEMA42 and VIRT_WRAPPER is used.

Recommendation is to use the Hardware Resource Isolation and Protection modules, which are described in chapters 8, 17 & 19 from the S32K3XX reference manual.

However, you can refer to the following application note: AN14715: Hardware Resource Isolation and Protection. Here is an excerpt from it, describing VIRT_WRAPPER initialization and usage:

1. In the RM module, check "RM Enable Virtual Wrapper feature" to enable VIRT_WRAPPER
   configuration.
2. In the Virtual Wrapper submodule, configure the virtual addresses and ownership domains for each pad and register.
3. In the XRDC module, assign the pad virtual addresses as peripherals to different domains.
4. In the Dio module, check "Dio VirtWrapper Support" to enable the VIRT_WRAPPER feature for Dio and assign a Virt_Wrapper PDAC to each Dio channel.
5. In the Port module, check "Port VirtWrapper Support" to enable the VIRT_WRAPPER feature for Port and assign a Virt_Wrapper PDAC to the MSCR and IMCR of each Port pin.
6. To ensure pad protection takes effect, follow the initialization order: 
   VIRT_WRAPPER initialization → PORT initialization → XRDC initialization.

I suggest reading the Usage and error handling of VIRT_WRAPPER section, it notes the steps for configuration.

Best regards,
Julián