Clock source of RUN mode selection

[1120905896]

After I set configuration of SOSC and SPLL. I start to select clock source of RUN mode and set core clock, bus clock and flash clock. But it shows different value of RCCR register and CSR register. Please see following capture. 

You can also find my source code of clock in the attachment.

MCU is S32K144.

IDE is IAR ARM 8.4.

Thanks for your attention.

Best regards,

Xiaowei.

[dianabatrlova]

Hello,

I have checked your code and you use |= when you set the clock source, but the SCS bit field is already configurated as Fast IRC (FIRC_CLK) by default.

The solution:

SCG->RCCR = SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(0x01) | SCG_RCCR_DIVBUS(0x01) | SCG_RCCR_DIVSLOW(0x03);

Also, you did not set SPLL dividers, please, refer to RM rev 11. Table 27-1. Clock descriptions.

hello_clocks_S32K144 example located in the S32DS can be useful for you.

I hope it helps.

Best regards,

Diana