Clock FIRC & PLL settings

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

Clock FIRC & PLL settings

1,066 次查看
Dev15
Contributor III

Hi Team,

I'm using RTD 3.0.0, S32K312, SDK 3.5 version and trying to configure PWM channels. The core clock is set to FIRC and could see a warning.

Dev15_0-1710865361390.png

 

Please help to resolve it.

Thank you

 

标记 (1)
0 项奖励
回复
1 回复

1,055 次查看
VaneB
NXP TechSupport
NXP TechSupport

Hi @Dev15 

As you select FIRC as the clock source you need to disable the PLL as mentioned in the warning. the warning would not be a problem. 

 

B.R.

VaneB

0 项奖励
回复