Clk2Cs parameter on Tresor issue

[MVR]

Hello everyone,

I'm trying to create a SPI code for S32K344 microcontroller using Tresos.

On RTD I was able to create without error (.mex file), but when I try to do the same configuration on Tresos, I got error.

The error shows that 1.0E-4 is out of range. But in the description it allow from 30ns up to 0.01s.

Can someone help me to fix this problem, please?

Thanks,

MVR

[NamLee]

Hi MVR,

I'm Nam from NXP RTD, i'm in charge of topic from Daniel so i comment directly here to discuss easier.

I saw the error came from Generate code, not Configure tool. The Configuration not report error, but the Generate value is not in range of delay time in PrescaledClock

About the value of TimeClk2Cs, it's the value of delay time in SCKPCS field, in range of 1~255 clock cycle which calculated with Prescaler as the field in TCR register.

The clock be calculated from Bus clock (which is 40M Hz if you not choosing Dual Clock of SPI), and the PrescalerValue is 2^(Prescaler) which calculated here:

With Busclock as 40M and DesiredBaudrate as 500K, the devide value should be 80, which mean the PrescalerValue is 1 (as 2^0) and the SckDiv will be 78.

I tried to enable the DesiredBaudrateConfig with corresponding values, confirmed it's correct.

So with PrescalerValue as 1, the PrescaledClock will equal with BusClock which is 40M Hz, and the Delaytime will have to in range of 2.5E-8 ~ 6.4E-6

As my view, i don't see problem with EB Config in my side, compare with RM of SPI.

I'm doubting about your configuration in DS (.mex file) in 2 points:

- Do you use DesiredBaudrateConfig and apply another Baudrate different with 500K? This might change the value of PrescalerValue.

- Your clock of SPI be changed somewhere.

Normally, the BusClock will be the reference clock which configured in this node, refered to Mcu

In case you enable DualClock mode, the BusClock will be BusClockAlternate

You should not enable the AlternateClockRef node.

Can you help me check these 2 points?

I have few questions with your DS tool configuration: 

- Do you use the same package RTD 4.0.0 HF01 in DS?

- In DS when you configure the value of Clk2Cs, can you give me the range of this node (in DS) in this time?

- In generated code, can you give me value of LPSPI_CCR_SCKPCS?

Thank you,

Nam.

[MVR]

Hello @NamLee , thank you by your support.

First of all, I'm facing error before to generate the code on Tresos:

Note:

- I attached the SPI and MCU modules configuration.

And answering your questions:

- Do you use DesiredBaudrateConfig and apply another Baudrate different with 500K? This might change the value of PrescalerValue.

R: I didn't use.

- In case you enable DualClock mode, the BusClock will be BusClockAlternate

R: I didn't enabled this option

- Do you use the same package RTD 4.0.0 HF01 in DS?

R: Yes and also I tested with the lastest version "4.00 HF02_D2407", which I get the same error.

- In DS when you configure the value of Clk2Cs, can you give me the range of this node (in DS) in this time?

R: Is it your request? ->

- In generated code, can you give me value of LPSPI_CCR_SCKPCS?

R:

Configuration that works (Generated by DS tool):

Configuration that doesn't work for me (generated by Tresos, with

Thanks,
MVR

[MVR]

Only complementing (I can't edit what I sent):
- Do you use DesiredBaudrateConfig and apply another Baudrate different with 500K? This might change the value of PrescalerValue.

R: I didn't use "DesiredBaudrateConfig" and also I didn't try to apply another baudrate.

[NamLee]

Hi MVR,

Thank you so much for your detailed answers.

It's not a configure tool issue because the value of node still in range, but invalid corresponding to the Clock and Baudrate.

Maybe in EB Tresos enable the feature Verify configuration everytime you change a node. It'll report errors before you hit generate.

But it doesn't matter. The root cause is the delay time is longer than maximum range.

I saw the value of CCR register, specially LPSPI_CCR_SCKPCS:

- The SCKDIV is 78, which confirm that the calculation of ScalerValue is correct here. Your configuration is fine.

- The SCKPCS/PCSSCK/DBT field is 255. Which is maximum of the range.

From my guess, in DS, if the configured delay value is higher than the possible delay time amount, then the code gen will set 255 as maximum value for those delay times.

I'll check the DS driver and code gen about this point.

In additionally, can you set the value of SpiTimeClk2Cs in EB to 6.4E-6? I suppose the generated code will be the same (with the code from DS), and all sequences will run normally.

Please help me to try this workaround. I'll also try in DS.

Thank you,
Nam.

[MVR]

Hello @NamLee,

It makes sense, as soon as possible I will try with 6.4E-6. Now I don't have more the hardware because it is being used in other place. But when I get back it I will test.

Also I will try to measure it. 

Thank you!

MVR

[NamLee]

Hi MVR,

I checked with RTD K3 4.0.0 RTM

The flow quite the same, when the SpiTimeClkCs value as input for GenerateExternalDeviceInfo function

And we have the same flow of generate value, as when the time is too high or too low, than the error be loged out.

In DS, when i set value Clk2Cs as 1.0E-5, the error reported. Because the range is maximum as 6.4E-6 (as calculation before)

Same flow with Cs2Clk. when i put it as 1.0E-6, value is in range and no errors reported.

To confirm about this, the generated values are matching with expectation

1> The SCKDIV is 78 -> as Scaler is 78 as calculation before. I'm using SLOW_CLK as 40M Hz for LPSPI2 channel

2> PCSSCK is 39 -> the delay time is 1/40M x (39 + 1) = 1.0E-6

3> SCKPCS is 0 as initialized value of Device.OptimalSCKPCS, only error log be updated.

From my view, there's no problem with driver in both EB Tresos and DS tool.

Thank you,

Nam.

[MVR]

Hey @NamLee ,

The SDK that I'm using is "S32K3_RTD_2_0_1_D2207_ASR_REL_4_4_REV_0000_20220707". So maybe this version has this problem, right?

So in the end, what value do these "255" represent?

I know that this is the maximum value, but how is the reverse calculation so I can find out the correct value to configure in Tresos?

Thanks,

MVR

[NamLee]

Hi MVR,

In my tested RTM 4.0.0, the error will be reported as i explained. I thought you're using RTD 4.0.0 also? Which is RTD_updatesite version that you're using right now? I'm using SW32K3_S32M27x_RTD_R21-11_4.0.0_D2311_DS_updatesite

One more point, please help me to check the implementation of SpiTimeClk2Cs code gen. It should be located in file C:\NXP\S32DS.3.5\eclipse\mcu_data\components\PlatformSDK_S32K3\Spi\Lpspi_Ip_PBcfg.c

I think you're using an old version, and the design at that time as i said, when you put a value higher than maximum then the register value will be set as 255, as in possible range.

The number stands for delay time required between Clock and Cs signal.

E.g: in my test, PCSSCK is 39 -> the delay time is 1/40M x (39 + 1) = 1.0E-6

With Busclock for LPSPI2 is 40M Hz.

So in 4.0.0, if you wanna keep the maximum delay time (as current sequence) then you just put the maximum value for those nodes (as 6.4E-6)

My point is, this is correct implementation in current design driver.

Thank you,

Nam.

[MVR]

Hello @NamLee 

I'm using SW32K3_RTD_4.4_2.0.1_DS_updatesite_D2207.

The problem is that when I define  1.0E-6, my application doesn't work... But when I define  1.0E-5 like the picture, it works but the SSCK is 255...

As I could understand with this old version, when selected a value out of range it is automatically set 255, right? So in the new version, which value should I set for my application works? Should be 1/40M x (255 + 1) = 6.4E-6?

I still doesn't have the hardware to test, but as soon as I receive back the hardware, I will test again.

Thanks,

MVR.

[NamLee]

Hi MVR,

- Yes. Seems like your version is old one. Can you help me to test with RTD_updatesite 4.0.0 in your side?

- Yes, for the 255 as maximum delay time you should put it as maximum in EB Tresos. The value range will be reported in the tool, so you can follow the range basically.

One more point, in the 2.0.1 that you're using, can you help me to share the file Lpspi_Ip_PBcfg.c? It should be located in Spi component of PlatformSDK in C:\NXP\S32DS.3.5\eclipse\mcu_data\components\PlatformSDK_S32K3\Spi\Lpspi_Ip_PBcfg.c

I wanna check the implementation of the SpiTimeClkCs.

Thank you,

Nam.

[MVR]

Hello @NamLee 

I will test with the new version. 

Sure, follow attached the .c that you requested. 

It is located in "C:\NXP\S32DS.3.4\eclipse\mcu_data\components\PlatformSDK_S32K3_2022_07\Spi"

Thank you!!

MVR

[NamLee]

Hi MVR,

I checked the file. This is an old implementation, so it's different with the RTD currently. Basically, the code not report any errors. It will set the minimum value (as 0) if you put delay time lower than minimum range, and set maximum value (as 255) if you put delay time higer than the maximum range.

When you put the delay time as 0, the code will immediately return 1, then the bestSckPcs will be 0 -> Register CCR_SCKPCR = 0

In case you put the value not 0 but lower than minimum range, the for loop will return with sckpcs = 1, due to the abs() function will increase when sckpcs increase.

Then the return value still 1, and bestSckPcs = 0 then.

As your case, when you put the value higher than maximum range, the abs() will lowest when sckpcs = 256. So the DeviceInfo of CCR will be 255, as your current code.

So from my opinion, for the current RTD driver, the errors is better (for customer), and you can set the maximum value of range for the 255 value of register CCR

As i said, you can see the tool automatically calculate the maximum range, also you can calculate it easily as my previous done one.

Thank you,

Nam.

[MVR]

Can someone help me, please? I closed the ticket but I found a new issue.

[danielmartynek]

Hi @MVR,

It has been reported to the RTD development team.

I will update the thread once I have some feedback.

BR, Daniel

[MVR]

Hello @danielmartynek 

Should I open a new topic? Thank you.

MVR

[danielmartynek]

Hello @MVR,

No need for a new thread.

But this case is currently pending on the RTD team, and it might take some time before it is analyzed by them and even longer to update the SW if needed.

[danielmartynek]

Hi @MVR,

What EB Tresos version do you use?

I can set 1.0E-4 in Tresos 29.

I imported this example:

...\SW32K3_S32M27x_RTD_R21-11_4.0.0_HF01\eclipse\plugins\Spi_TS_T40D34M40I0R0\examples\EBT\S32K3XX\Spi_Transfer_S32K344

Regards,

Daniel

[MVR]

I'm using 29 as well. That's strange...

[danielmartynek · Accepted solution]

I see now, I can reproduce it.

The range that the tool reports depends on the selected clock and baudrate.

So, if you change the baudrate, you should see that the range moves.

The delay is configurable in the CCR register and it depends on TCR[PRESCALE].

Regards,

Daniel