Hi NXP Community,
I’m working on a project using the S32K358 and have a couple of general clarifications regarding dual-core (Core0 and Core2) behavior, particularly around peripheral and interrupt access. Based on my observations, I’d like to confirm the following points or understand if there are any known limitations or workarounds:
Q1: Interrupt Vector Access (e.g., PIT0_IRQn)
Is the interrupt vector/handler specific to each core?
For example, if I configure and use PIT0_IRQn in Core0, I am unable to access or use the same interrupt in Core2.
Is this expected behavior due to interrupt routing or core-specific limitations? Can the same interrupt be handled by both cores, or only one?
Q2: SIUL2 Pin Input Access from Multiple Cores
If I configure a pin (e.g., through SIUL2) as a digital input in Core0, is it possible to also configure and read the same pin in Core2?
Will both cores be able to read the same input pin simultaneously, or should only one core handle this configuration and access?
I tried configuring the same pin for input on both cores and did not encounter any hard faults or build-time errors, but I want to be sure if this is a supported use case or if it could cause issues at runtime.
I would appreciate any clarification or documentation references you can provide on these multi-core interaction aspects. If there are recommended best practices or limitations, that would also help in planning the architecture accordingly.
Thanks in advance!
