Clarification on CAN0 pin combinations in S32K311

[yusupkhan241]

Hi NXP Team,

I am working on the NXP S32K311 and need clarification regarding CAN0 pin multiplexing. From the reference manual and pin configuration tools, I understand that CAN0 can be routed through specific pin pairs such as:

• PTB0 (CAN0_RX) and PTB1 (CAN0_TX)
• PTC2 (CAN0_RX) and PTC3 (CAN0_TX)

In our current hardware design, CAN0 is connected using:

• PTB0 as CAN0_RX
• PTC3 as CAN0_TX

Observation:

• CAN communication works intermittently
• Errors (CRC/ACK/bit errors) are observed under certain conditions
• Behaviour varies across boards

Questions:

1. Is mixing CAN0 RX and TX pins across different groups (e.g., PTB0 + PTC3) a supported configuration on S32K311?
2. If not supported, could you confirm that this may lead to intermittent or undefined CAN behaviour?
3. Are there any internal routing or SIUL2 limitations that require RX/TX to be selected strictly from the same pin pair?

We require above information from you to validate this as the root cause of the observed issue.

Thanks in advance for your support S32DS-ARM S32K31XEVB-Q100

[PetrS]

Hi,

1. Is mixing CAN0 RX and TX pins across different groups (e.g., PTB0 + PTC3) a supported configuration on S32K311?
A: yes, this is possible. Those pins are different pad types, but it should not be an issue, considering pin rates etc

2. If not supported, could you confirm that this may lead to intermittent or undefined CAN behaviour?

3. Are there any internal routing or SIUL2 limitations that require RX/TX to be selected strictly from the same pin pair?
A: you should properly set the MSCR and IMCR registers to select desired functionality on used pin
TX on PTC3: set MSCR67 OBE=1, SSS=3
RX on PTB0: set MSCR32 IBE=1 and IMCR0.SSS=3 

BR, Petr

[db16122]

S32k3:Can - NXP Community

[yusupkhan241]

We observe that CAN0 is currently configured using PTB0 (RX) and PTC3 (TX), i.e., signals are selected from different pin groups.

Based on observed intermittent communication errors (CRC, ACK, bit errors), we suspect that mixing RX/TX across different pin groups may not be a validated or recommended configuration on NXP S32K311.

Could you please confirm whether CAN RX and TX must be selected strictly from the same predefined pin pair (e.g., PTB0/PTB1 or PTC2/PTC3) due to SIUL2/internal routing constraints?