Clarification Required on PWM Pin Mapping Approach for S32K312

[SHIVAKUMAR55]

Hi Team,

In our motor control development with the S32K312 100-pin MCU, we are considering the below two PWM output mapping approaches.

Method-1 uses eMIOS channels along with LCU-based outputs:

• PTA0 -  PWMU_HS -  eMIOS_0_CH[17]_Y - LCU0_OUT4
• PTA1 -   PWMU_LS -   eMIOS_0_CH[9]_H - LCU0_OUT5
• PTA2 -  PWMV_HS -  eMIOS_1_CH[19]_Y - LCU0_OUT3
• PTA3 -  PWMV_LS -   eMIOS_1_CH[20]_Y - LCU0_OUT2
• PTD2 -  PWMW_HS - eMIOS_1_CH[21]_Y - LCU0_OUT1
• PTD3 -  PWMW_LS -  eMIOS_1_CH[22]_X - LCU0_OUT0

Method-2 uses another PWM mapping option:

• PTB16 -  PWMU_HS -  eMIOS_0_CH[4]_G
• PTB13 -  PWMU_LS -   eMIOS_0_CH[1]_G  - LCU0_OUT3
• PTB17 -  PWMV_HS -  eMIOS_0_CH[5]_G
• PTB14 -  PWMV_LS -   eMIOS_0_CH[2]_G - LCU0_OUT7
• PTB1 -    PWMW_HS - eMIOS_0_CH[7]_G
• PTB0 -   PWMW_LS -  eMIOS_0_CH[3]_G - LCU1_OUT5

We need some more clarity from the NXP side regarding which PWM mapping approach should be selected and what the practical effects or limitations are for each method.

Please advise on the following points:

• Which method is recommended for motor control applications?
• What are the advantages and disadvantages of each approach?
• Are there any considerations related to synchronization, dead-time insertion, ADC triggering, fault handling, or LCU/TRGMUX usage?
• Are there any software or hardware limitations that we should consider before finalizing the design?

Please share your recommendations based on your experience and reference designs.

Regards,
Shiva

[SHIVAKUMAR55]

Hi @VaneB,

For the S32K312 100-pin MCU, we are considering the below PWM pin mapping option:

Pin Net Name Phase  Side eMIOS Channel LCU Output
PTA0    PWMU_HS  -    U High-side   eMIOS_1_CH[6]_H    LCU0_OUT6
PTA1     PWMU_LS   -     U Low-side   eMIOS_1_CH[15]_H    LCU0_OUT11
PTA2    PWMV_HS -    V High-side    eMIOS_1_CH[19]_Y    LCU0_OUT3
PTA3    PWMV_LS  -    V Low-side     eMIOS_1_CH[20]_Y   LCU0_OUT2
PTD2    PWMW_HS -   W High-side   eMIOS_1_CH[21]_Y    LCU0_OUT1
PTD3 PWMW_LS -    W Low-side       eMIOS_1_CH[22]_X   LCU0_OUT0

In this method, all six PWM outputs are mapped through the same eMIOS_1 instance. We believe this may be beneficial for synchronization and motor-control PWM generation.

Please confirm if this understanding is correct.

Also, please clarify the meaning and impact of the eMIOS channel types H, Y, and X in this configuration. We would like to understand whether these channel types have any major impact on PWM generation, synchronization, dead-time control, ADC triggering, or LCU TRGMUX usage.

Please review and guide us on whether this PWM pin mapping is suitable for our motor-control application.

Regards,
Shiva

[VaneB]

Hi @SHIVAKUMAR55 

Method 2 keeps all PWM channels within a single eMIOS instance, which gives you a shared time base and makes it much easier to achieve clean phase alignment and simpler timing overall.

On the other hand, Method 1 spreads the channels across multiple eMIOS instances and routes them through the LCU, following a structure similar to the eMIOS → TRGMUX → LCU approach used in the S32K344 3‑phase sensorless PMSM motor control reference design. This setup can be very helpful if you need more flexibility, such as advanced output conditioning, dead-time control, or adding fault-handling features later on.

That said, Method 1 does come with a bit more configuration effort and less synchronization because it uses multiple eMIOS instances. In practice, a good approach is to start with Method 2 for its simplicity and solid timing behavior, and only move to an LCU-based solution like Method 1 if your design later requires more advanced control or safety features.

For additional guidance, it is recommended to refer to the 3‑phase Sensorless PMSM Motor Control Kit with S32K344 application notes and associated software:

S32K344 Brushless Direct Current and Permanent Magnet Synchronous Motor Control Development Kit (MCS...

BR, VaneB