- In S32K144 RM , Page 1008, Table 38-4 Module operation in available power modes (continued)
It says ADC stays OFF in VLPS. As per my observations, we can see ADC interrupt in VLPS(I had a small experiment in which I moved to VLPS from RUN and again moved back to RUN on ADC interrupt with EVB). How does it work here?
If this is the case, then will PDB be also able to give interrupt in VLPS? (PDB is marked as OFF in Reference manual)
Additionally,In my case , SIRC clock is selected for ADC0. Is it in working condition because of it? As SIRC clock is marked as FF in same table. Please share some inputs on this. What would I need to do to make sure ADC0 is non functional in VLPS ? ex. clock selections
PDB is OFF in VLPS since the PDB functional clock is SYSCLK.
Let me confirm the ADC functionality in VLPS.
I will update this thread once I have more information.
One quick question in a mean while, "PDB functional clock is SYSCLK" , to confirm this I checked the clock_manager configuration settings in Processor Expert.
Settings->Peripheral Clocks->PDB0_CLK->Interface Clock is set to SYS_CLK in a same way, for ADC0_CLK interface clock is set as BUS_CLK.
Can we possibly change the Interface clock for peripherals ? Or this interface clock is fixed for S32K1XX (S32K144 in my case) peripherals and we have a flexibility just to functional clock based on power mode? Below is my clock configuration :
It shows PDB0_CLK interface clock as SYS_CLK and no functional clock, can you please share difference between Interface clock and functional clock in this case. I would be helpful.
Any additional inputs on this will be helpful for me. Thank you.
Please refer to Table 27-9. Peripheral module clocking, RM. rev.9
Interface clock is for the bus interface, if this clock is disbled, any access to the modele triggers a bus fault exception.
ADC functional clock is the clock of the ADC converter.
PDB has only one clock for both the interface and the timer.
Thanks for this pointer Daniel.
As per my understanding, Functional clock is responsible for ADC to keep converting data. Bus clock is responsible for communicating this data to other peripherals(not sure if conversion done interrupt is raised when BUS_CLOCK is not available?).
With this understanding, can you please confirm, we want ADC to be functional in VLPS, what clocks should be ideally assigned as a functional and interface clock. Same question is for PDB ?
Please correct my understanding, if it's wrong. Thank you.
I'm still waiting for more information about the ADC in VLPS.
The ADC interface CLK is always the BUSCLK, as you can see above in the table.
PDB cannot be used in VLPS for sure.
NVIC is OFF in stop modes, but there is AWIC active instead which detects asynchronous wake-up events in stop modes and then signal to clock control logic to resume system clocking.
Table 2.3 Core modules, RM rev.9
The ADC functionality in VLPS was not validated.
We can't guarantee a proper funtionlity of this module in VLPS.
And therefore, ADC must be OFF in this low-power mode.