There is an issue with CAN data loss when receiving. That is, I have made a counter in the receive interrupt to count up how many CAN message that received by the chip. From the result, it seems that there are loss even under low load. Please help identify issue. Thank you.
Hello and thank for you interest in using MBDT,
Having your Simulink model attached to this post would allow us to better understand the issue but still, there are a few general things to consider when using the CAN communication blocks for receiving messages.
1) Please make sure that you have multiple CanHardwareObjects configured in your configuration project. If available resources allow it, there could be one for each Can ID in the network, for better performance.
A CanHardwareObject can be configured to accept only certain Can IDs by setting the CanHwFilters in your configuration project (EB Tresos or S32 COnfiguration Tools)
2) If you are using CanHardwareObjects with Polling processing type (not recommneded for high loads), in addition to the suggestion from point 1), the Fixed-step size can be reduced in order to better handle the incoming messages.
Hi @Adrian_Gherca ,
Thanks for your quick response, I have attached the model along with its configuration.
I have created a test to calculate receive counter for each CAN and output in the UART.
The result show that CAN0 receive the exact amount, however, CAN 1, 2, 3 are not having the correct number of receive counter. CAN 1 have received less than it sent, CAN 2 and CAN 3 have received more then it sent.
In the CAN controller configuration, 0, 1, 2, is for CAN 0 with different setting 3, 4, 5, 6, 7 is for CAN 1, 2, 3, 4, 5. Does adding more CAN hardware object here like CAN 0 for all the other CAN would resolve the issue?
I have added CanRxFiFo in canController for CAN 1, 2, 3, 4, 5 with the following set up.
Is the setting correct for using legacy RxFIFO?
We are not planning to use polling, and hope that interrupt and RxFIFO can help resolve the issue mentioned above. Thanks!
Hello,
I see that you are using the Hardware Interrupt Callback block set for CanIf_RxIndication for receiving the CAN messages and then a Uart_SyncSend block for sending the messages further.
Here are a few things to consider to improve this transfer:
1) In this scenario you are using two different communication protocols for monitoring the CAN messages traffic. Depending on your configuration project it might be the case that the UART transmission works at a slower speed than the CAN reception.
2) You can try doing a synchronization between the CAN and UART commuication blocks. In the IRQ Handler callback subsystem RX_Complete_Event
call the UART_SyncSend block directly in the interrupt of the CAN RX_Complete_Event callback:
I have updated a version to observe data through FreeMaster so that it's more clear to describing the issue.
Here's what my model now looks like:
Here's what inside can_out subsystem
We speculate that CAN2 and CAN3 will sometime received data that was meant for CAN0 and CAN1, when all four CAN and sending. This is chart is used to mainly calculate how many receive CAN message coming in from each CAN and how many times does a CAN received message that shouldn't be receiving. This test is to show that data integrity is lost when all 4 CANs are actively receiving.
Test1, CAN0 and CAN1 only:
in this case, everything works as expected, we can see that the number of transmit and received match for when only CAN0 and CAN1 are active.
Test2, CAN2 and CAN 3 only:
In this case, everything work as expected, CAN2 and CAN3 are receiving the exact amount be sent.
Test3, CAN0, CAN1, CAN2, and CAN 3:
In this case, we noticed that there are many error when all 4 CAN being active. we noticed that there are controller ID and hardware ID are being mixed incorrectly, that is we are expecting following:
ControllerID | 0 | 1 | 2 | 3 | 4 | 5 |
CanHardwareObjectID | 2 | 3 | 4 | 5 | 6 | 7 |
But if this is not the case, then ctrlErrorOut counter increase.
Furthermore, we added ID error test by checking source address for each CAN ID received, that is:
CAN | 0 | 1 | 2 | 3 |
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Source Address | 0x01 | 0x02 | 0x03 | 0x04 |
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And if this is not the case, we will consider there is ID error from the receiving side.
The same test is also done to check if data are received as expected by checking the first byte for each CAN. and we expect the following:
CAN | 0 | 1 | 2 | 3 |
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Data(1) | 0x01 | 0x02 | 0x03 | 0x04 |
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As we can see from test 3 image, controllerId and hardwareId does not match in occurred 42 times, and ID error in occurred 60 times, and Data error occured 98 times. So at least in this configuration, we are observing that CAN2 and CAN3 are being interfered by CAN0 and CAN1, causing data corruption and losing data integrity.
I have attached the project, let me know if there is any issue, thanks!
We also tried enable FIFODMA, however, we are running into issue with the configuration. Let me know how to correctly enable DMA. Thanks!
