Hi,
I have configured PTA12 pin as CLKOUT_STANDBY (SSS = 3).
Attached tou can find the registers configuration.
From oscillo, I don't see the clock.
The code:
void STARTD_SetClkOutStandby(STARTD_ClkOutCfgStandby_t cfg, uint8_t divider)
{
/*==== START_USER_CODE Don't change this comment ===*/
/*-E> safe MC3.R11.4 1 No cast issue since pointer refers to uC memory address */
MC_CGM_Type * const Startd_MCCGMInstance = IP_MC_CGM;
/* clock source selection status */
uint32_t selctl = 0u;
uint8_t div;
/* make sure divider is within ranges */
SYSM_ASSERT((divider < 9u) && (divider > 0u));
/* configure pin PTD10 */
/* Clear the OBE bit field */
Startd_Siul2Instance->MSCR[12u] &= ~SIUL2_MSCR_IBE_MASK;
/* Write t he OBE bit field */
Startd_Siul2Instance->MSCR[12u] |= SIUL2_MSCR_IBE(0U);
/* Clear the OBE bit field */
Startd_Siul2Instance->MSCR[12u] &= ~SIUL2_MSCR_OBE_MASK;
/* Write the OBE bit field */
Startd_Siul2Instance->MSCR[12u] |= SIUL2_MSCR_OBE(1U);
/* Set the SSS bit field */
Startd_Siul2Instance->MSCR[12u] &= ~SIUL2_MSCR_SSS_MASK;
/* Write the SSS bit field with mux */
Startd_Siul2Instance->MSCR[12u] |= SIUL2_MSCR_SSS(3u); /* SSS = 0011b */
/* Software controlled clock switch request */
Startd_MCCGMInstance->MUX_5_CSC &= ~MC_CGM_MUX_5_CSC_CG_MASK;
Startd_MCCGMInstance->MUX_5_CSC |= MC_CGM_MUX_5_CSC_CG(1U);
/* Check clock at the output of the clock mux is gated to logic-0 */
while (((Startd_MCCGMInstance->MUX_5_CSS & MC_CGM_MUX_5_CSS_CS_MASK) >> MC_CGM_MUX_5_CSS_CS_SHIFT) == 1U) {}
/* If there is something to output...*/
if(cfg != STARTD_CLKOUT_STANDBY_DISABLED)
{
switch(cfg)
{
case STARTD_CLKOUT_STANDBY_AIPS_SLOW_CLK:
selctl = 23u;
break;
case STARTD_CLKOUT_STANDBY_FXOSC_CLK:
selctl = 2u;
break;
case STARTD_CLKOUT_STANDBY_SIRC_CLK:
selctl = 1u;
break;
case STARTD_CLKOUT_STANDBY_FIRC_CLK:
selctl = 0u;
break;
default:
/* no operations */
break;
}
}
/* select input clock source */
Startd_MCCGMInstance->MUX_5_CSC &= ~MC_CGM_MUX_5_CSC_SELCTL_MASK;
Startd_MCCGMInstance->MUX_5_CSC |= MC_CGM_MUX_5_CSC_SELCTL(selctl);
/* Clear CG and FCG bit after set the SELCTL bit */
Startd_MCCGMInstance->MUX_5_CSC &= ~(MC_CGM_MUX_5_CSC_FCG_MASK | MC_CGM_MUX_5_CSC_CG_MASK);
/* enable and select divider */
/* the effective divider is -1 the input value */
div = divider - 1u;
Startd_MCCGMInstance->MUX_5_DC_0 &= ~MC_CGM_MUX_5_DC_0_DIV_MASK;
Startd_MCCGMInstance->MUX_5_DC_0 |= (MC_CGM_MUX_5_DC_0_DIV(div) | MC_CGM_MUX_5_DC_0_DE(1U));
/* Wait until divider configuration update has finished */
while (((Startd_MCCGMInstance->MUX_5_DIV_UPD_STAT & MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_MASK) >> MC_CGM_MUX_5_DIV_UPD_STAT_DIV_STAT_SHIFT) == 1U) {}
/* Check clock at the output of the clock mux is present */
while (((Startd_MCCGMInstance->MUX_5_CSS & MC_CGM_MUX_5_CSS_CS_MASK) >> MC_CGM_MUX_5_CSS_CS_SHIFT) == 0U) {}
/*==== END_USER_CODE Don't change this comment ===*/
}
Can you hel me?
Thank you.
