Hi @Embedded_novice
Sorry for the misunderstanding, and thank you for the clarification.
It is not strictly necessary to configure the CLK pin as high in the Port driver, since it is managed by the SPI driver.
I performed a test on my side using the S32K148EVB and the Spi_Transfer_S32K148 example. I modified the configuration so that the CLK pin is driven high by the Port driver and also set SpiShiftClockIdleLevel to HIGH. With these changes, I did not observe the behavior you described. Could you please try running the same example with these modifications and let me know if the behavior changes on your setup?