CAN Message ID Filter concept

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CAN Message ID Filter concept

1,208 Views
Dileep1441
Contributor I

Hi,

I want to use CAN Message ID filter concept using  FLEXCAN_DRV_SetRxMbGlobalMask(a,b,c);

1)MSG ID range:: 0x18c to 0x48C-->What is the required filter value for this range?.

2)MSG ID range:: 0x600 to 0x605-->What is the required filter value for this range?.

3)MSG ID range:: 0x401 to 0x406-->What is the required filter value for this range?.

4)MSG ID range:: 0x333 to 0x339-->What is the required filter value for this range?.

 

Also please explain the filter concept, how to do the calculation for required range of message ID's.

 

Software:S32 Design Studio for ARM Version: 2018.R1

MCU:S32K144

 

Thanks in Advance.

 

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

none of your desired ID ranges can be simply implemented using single RX Message buffer. 

Matching to a range of IDs is possible by using ID acceptance masks. FlexCAN supports individual masking per MB (IRMQ bit set) or global masking scheme (IRMQ cleared). During the matching algorithm, if a mask bit of mask register is asserted, then the corresponding received ID bit is compared with the ID bit defined in the MB or RXFIFO filter table. If the mask bit is negated, the corresponding ID bit is a "don't care".

You can refer to below demo;
https://community.nxp.com/t5/S32K-Knowledge-Base/S32K1xx-FlexCAN-Mask-Setting-Demo/ta-p/1519753

BR, Petr

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1,182 Views
Dileep1441
Contributor I

Hello @PetrS ,

Thanks for the quick response,

actually in my project we are using can_pal_s32k144 example, and masking purpose we are using 

FLEXCAN_DRV_SetRxMbGlobalMask(a,b,c); API.

Can you please share the direct masking value atleast for the below ID ranges.

1)MSG ID range:: 0x18c to 0x48C-->What is the required filter value for this range?.

2)MSG ID range:: 0x600 to 0x605-->What is the required filter value for this range?.

Also can you please explain the masking method clearly with the example range of ID 0x600 to 0x605.

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1,111 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

first I can recommend to use individual masking scheme. That way you will be able to create more masks, each MB has its own mask.

ID rage 0x600 to 0x605 cannot be done by single MB and mask. Assume you set MBs std ID as 0x600
Then if you set mask as 0x7FC, then 2 lower ID bits are don't care, so MB will be able to receive IDs 0x600-0x603.
For mask 0x7F8, lower 3 bits are don't care, MB receives IDs 0x600-0x607.

BR, Petr

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1,104 Views
Dileep1441
Contributor I

Hello @PetrS ,

Thanks for the reply.

 

As per your previous reply, for mask 0x7F8, lower 3 bits are don't care, MB receives IDs 0x600-0x607.

means 

0110 0000 0000
0110 0000 0111
---------------------
0111 1111 1000==>0x7F8(Last 3 bits(0-2) must be 0 because of don't care, Ex-NOR operation need to do for remining bits from 3 to 10) right?

 

If the above scenario is correct then for 0x18c,0x28c,0x38c and 0x48c

0000 0001 1000 1100
0000 0100 1000 1100
-----------------------------
0000 0000 1111 1111==>0X0FF(is this mask value is fine)?

or else i need to configure different MB's with individual ID's 0x18c, 0x28c,0x38c,0x48c or any better way of masking method is there?

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

to accept incoming message a received ID must match with configured one in the MB. A mask bit specify if respective bit must match or is don't care.

So for 1st example configuring MB ID to have value from 0x600-0x607 range and using mask 0x7F8, the MB accepts messages with 0x600-0x607 IDs.

For 2nd example to receive just 0x18c,0x28c,0x38c and 0x48c IDs a 3 separate MBs will be needed I think, with following setting
MB ID 0x18C, mask 0x5FF, MB accept 0x18C and 0x38C IDs
MB ID 0x28C, mask 0x7FF, MB accept 0x28C ID
MB ID 0x48C, mask 0x7FF, MB accept 0x48C ID

BR, Petr

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