CAN (FlexCAN) mailboxes on S32K358 — IFLAG bits

[kavyakoney]

Hi all,

I’m working with the S32K358 FlexCAN module and I want to confirm correct register/flag usage and the safe procedure for configuring 64 hardware message buffers (MB0..MB63) as receive mailboxes. I read the RM but I want to make sure I understand the practical behaviour,

I want to know which registers / flags indicate FIFO state, mailbox interrupt flags, overflow/warning, and the recommended read/clear sequence for MBs when using 64 MBs.

should I enable per-MB interrupt masks (IMASK) for all MBs or use a grouped approach, read IFLAG1/IFLAG2 in ISR and process flagged MBs in a loop? Any concerns about ISR duration and priority?

How does mailbox overwrite manifest in flags/registers if I miss reads (i.e., if a new frame arrives into the same MB before I read the old one) — is there a flag? If not, how to detect that an overwrite happened?

I tried to recieve CAN data and it is using only MB0 for all CAN frames. is it fixed?

Can anyone please explain about Flexcan mailboxes and what to do if i want use 64message buffers and what i have to check in the registers?

[PetrS]

Hi,

most of questions can be addressed by reading chapters 73.3.4 Receive process and 73.3.5 Matching process of the device RM. Below is quick feedback for questions you put

Q: I want to know which registers / flags indicate FIFO state, mailbox interrupt flags, overflow/warning, and the recommended read/clear sequence for MBs when using 64 MBs.
A:
Legacy RX FIFO mode uses MB0–MB5 as a receive queue. Moreover MB6-MB7 (or more, depending on filter table configuration, CTRL[RFFN]) is used to specify ID filter table. So if you enable legacy RX FIFO, you cannot use all 64 MBs as independent mailboxes. Unless you will use FlexCAN instance that have up to 96MBs, FlexCAN0-2. Or enhanced RX FIFO is used.
If legacy RX FIFO is enabled, MB0 is the FIFO entry point, user is using MB0 to read messages.

Registers and Flags to Monitor
IFLAG1 / IFLAG2: Interrupt flags for MB0–MB31 and MB32–MB63.
IMASK1 / IMASK2: Per-MB interrupt enable masks.
If legacy RXFIFO enabled
RXFIR: Indicates which FIFO entry was filled.
IFLAG1[BUF5I] (Frames Available in Legacy RX FIFO) - set when at least one frame is available to be read from the Legacy FIFO.
IFLAG1[BUF6I] (Legacy RX FIFO Warning) - set when the Legacy RX FIFO receives a new message that increases the number of unread messages from four to five. This change means that the Legacy RX FIFO is almost full. The flag remains set until the CPU clears it.
IFLAG1[BUF7I] (Legacy RX FIFO Overflow) - set when an incoming message is lost because the Legacy RX FIFO is full.
If the corresponding mask bits are set, an interrupt is generated.

Q: should I enable per-MB interrupt masks (IMASK) for all MBs or use a grouped approach, read IFLAG1/IFLAG2 in ISR and process flagged MBs in a loop? Any concerns about ISR duration and priority?
A:
Recommended ISR Strategy
There is common interrupt vector for 32MBs (0-31, 32-64, ...)
Enable interrupts for all MBs you care about, then in ISR: Read IFLAG1 or IFLAG2. For each set bit, process that MB. Clear the flag by writing 1 to the bit (write-1-to-clear).
If you loop through 32 MBs in ISR, it can be long, but it is application concerns.

Q: How does mailbox overwrite manifest in flags/registers if I miss reads (i.e., if a new frame arrives into the same MB before I read the old one) — is there a flag? If not, how to detect that an overwrite happened?
A:
Overwrite Detection
FlexCAN does NOT have a dedicated overwrite flag for MBs. If a new frame arrives before you read the old one, the old data is lost silently. The interrupt flag (IFLAGx) just stays set until cleared.
Only the MB’s Control/Status word CODE filed is changed to OVERRUN

Q: I tried to receive CAN data and it is using only MB0 for all CAN frames. is it fixed?
A:
Your observation that “all frames go to MB0” usually means:
RX FIFO is enabled, and MB0 is the FIFO entry point.
Or your acceptance filters are set so only MB0 matches.

BR, Petr