While working with SW32K3_RTD_4.4_2.0.0 intergrated with Vector's AUTOSAR stack for S32K344 chip, we found a bug in Port driver related to Adc driver configuration.
In function Siul2_Port_Ip_WriteDCMConfiguration:
the call of PORT_WRITE32 is unconditional, executed always, therefore overriding previous configuration(s).
We had to move this call and therefore modify this function in Siul2_Port_Ip.c as follows:
With such a hotfix, the ADC driver works correctly.
Please consider this finding in the next release of SW32K3_RTD.
Lets check original code...
Register DCM_DCMRWF4_ADDR32
Configuration (generated):
Original code
enums (0x0xxx causes set proper bit, 0xFxxx causes clear proper bit)
defines (DCM_DCMRWF4_ADC_INTERLEAVE_MASK represents all MUX_MODE bits)
Code with comments:
Final result:
- all MUX_MODE are set to '1' regardless of configuration !
- bits 16..31 (used 16..18 e.g. for glitch) are always cleared
Solution1:
As mentioned in Artur's message
dcmrwf4RegValue &= (adcInterleaves | (~DCM_DCMRWF4_ADC_INTERLEAVE_MASK));
Protects bits 16..31
PORT_WRITE32(DCM_DCMRWF4_ADDR32, dcmrwf4RegValue);
Correct write operation. This is called only once, because adcInterleaves size is always 2 and when one is set then second is always '0':
.adcInterleaves = {
MUX_MODE_EN_ADC2_S9_0,
MUX_MODE_NOT_AVAILABLE // 0
},
Solution2:
Original code with change:
typedef enum
{
MUX_MODE_NOT_AVAILABLE = 0x0000UL, // unsigned long
MUX_MODE_EN_ADC1_S14_1 = 0x0008UL,
MUX_MODE_EN_ADC1_S15_1 = 0x0010UL,
MUX_MODE_EN_ADC0_S8_1 = 0x0002UL,
MUX_MODE_EN_ADC2_S8_1 = 0x0200UL,
MUX_MODE_EN_ADC0_S9_1 = 0x0004UL,
MUX_MODE_EN_ADC2_S9_1 = 0x0400UL,
MUX_MODE_EN_ADC1_S22_1 = 0x0020UL,
MUX_MODE_EN_ADC1_S23_1 = 0x0040UL,
MUX_MODE_EN_ADC1_S14_0 = 0xFFFFFFF7UL, // added FFFF to protect bits 16..31
MUX_MODE_EN_ADC1_S15_0 = 0xFFFFFFEFUL,
MUX_MODE_EN_ADC0_S8_0 = 0xFFFFFFFDUL,
MUX_MODE_EN_ADC2_S8_0 = 0xFFFFFDFFUL,
MUX_MODE_EN_ADC0_S9_0 = 0xFFFFFFFBUL,
MUX_MODE_EN_ADC2_S9_0 = 0xFFFFFBFFUL, // this case
MUX_MODE_EN_ADC1_S22_0 = 0xFFFFFFDFUL,
MUX_MODE_EN_ADC1_S23_0 = 0xFFFFFFBFUL,
} Siul2_Port_Ip_AdcInterleaves;
And of course in the same place as in original code correct write operation:
PORT_WRITE32(DCM_DCMRWF4_ADDR32, dcmrwf4RegValue);
