AD9833 LPSPI bus configuration with S32k358

[soumik1506]

Hello,

I am using the AD9833 chip to generate a 100kHz sine wave using the data coming from the SPI bus configured in my S32k358 microcontroller. I have set the SPI bus using the LPSPI RTD driver. I have defined a function that sets the FSYNC pin low, pushes the data and the sets the FSYNC pin back to high. I have attached my LPSPI configuartions

Based on the configuration, i am able to get the SPI wavforms, butstill the control register of the DAC is not getting set.

As per the datasheet and application note AN-1070 following is my code to manipulate the equivalent data into the DAC:

DAC_data_send(0x2100); //RESET ON
data = 1073742;//100000Hz equivalent 16 bit data from SPI2 MOSI
uint16 MSB = (uint16)((data & 0xFFFC000) >> 14); // extracting MSB and setting control bits for FREQREG0
uint16 LSB = (uint16)(data & 0x3FFF); // extracting LSB and setting control bits for FREQREG0

LSB |= 0x4000; // Control bits for LSB for FREQREG0, 0x8000; // Control bits for LSB for FREQ1
MSB |= 0x4000; // Control bits for MSB for FREQREG0, 0x8000; // Control bits for MSB for FREQ1

DAC_data_send(LSB); //Writing 14 bit LSB to Freq Register 0
DAC_data_send(MSB); //Writing 14 bit MSB to Freq Register 0
DAC_data_send(0xC000); // Setting Phase Adjustment in the Phase Register 0
DAC_data_send(0x2000); // RESET OFF*/

The value 1073742 is by this calculation - (100000*2^28)/(25*10^6). I have followed the formula given in the datasheet. I dont know where i am going wrong, can someone point me out

[Robin_Shen]

Hi

Since AD9833 is not a product of NXP, I don't know much about it. I read its manual and found that the following highlighted part needs to be modified.

Did you connect FSYNC to PCS0? According to my understanding, FSYNC pin should be the Chip Select pin of SPI.

Please use a logic analyzer to capture the SPI communication waveform. If you have used AD9833 before and are familiar with its control, it is recommended to observe the SPI waveform to check whether it is correct.

Best Regards,
Robin
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[soumik1506]

Yes i have connected the FSYNC pin of the AD9833 chp to LPSPI-PCS0 pin. I am getting SPI sout, serial clock and Chip select at the AD9833 pins.

Even after making the changes you have highlighted in the images,  i am still not getting output from the AD9833 VOUT pin. I have tried with different FREQREG values

[Robin_Shen]

Have you refer to AD9833 - Microcontroller No-OS Driver?
https://github.com/analogdevicesinc/no-OS/blob/main/drivers/frequency/ad9833/ad9833.c
https://github.com/analogdevicesinc/no-OS/blob/main/drivers/frequency/ad9833/ad9833.h
Please use a logic analyzer to check whether the SPI sent to AD9833 is correct.

[soumik1506]

I went trough it, but i want to do the data transfer using the LPSPI bus configuration. I have verified that my data is getting transmitted via the SPI bus, but when i am send the data as per the order defined in the No-OS driver, i am able to get the sine wave with the rated output  voltage, but not able to control the frequecny. The AD9833 chip's vout voltage frequency is equal to the SPI SCLK not the frequency set in the FREQREG. Please tell me where i am going wrong.

Soumik

[Robin_Shen]

Are you saying that the AD9833 is OK with all SPI commands except receiving the FREQREG register?

Since you are referring to AN-1070: Programming the AD9833/AD9834, have you considered using the same SPI Command Sequence and only modifying the frequency part? At the same time, use a logic analyzer to capture the SPI waveform to ensure that it is consistent with AN-1070?

[soumik1506]

I have referred the AN1070 application, followed the steps as it is explained in the article. I am not getting the correct output.

My logic analyser is not working properly, i am using the usual probes. I am able to decode the SPI sout, PCS0 and SCLK, but when i measure the output frequency of the AD9833 Vout pin, it keeps changing few values near to the frequency i have set, and to one/two frequencies which are way more than the set value.

When i see examples where the same AD9833 chip is programmed with different platform board, the frequency of the wave form is exactly equal to the frequency set.

I have also gone through the No-OS driver codes specific for this chip and i have defined functions that similar to the definitions in the source code. Wherever there were statements with no_spi and no_gpio, i have replaced them with Lpspi and Siul2_gpio functions.

I have tested them and i am getting similar output. I still dont know what i am missing out here.

[Robin_Shen]

Since PTB3 is connected to J63 pin8 (GMAC_RGMII_TXD3_PTB3) by default on the S32K3X8EVB-Q289 board, it is not convenient for me to test it on the S32K3X8EVB-Q289.
Today I found another S32K358 mini board to test your project. The following is the SPI data captured by the logic analyzer. I feel that this data is a bit strange, and the time interval for sending SPI data is too short. I don't know if your application really needs to modify the output of AD9833 so frequently.

[soumik1506]

Then what must be the SPI Bus Time and clock configurations. I have made sure to select the 40MHz clock for my SCLK (as stated in the Datasheet).

As per the timing characteristics in the datasheet, the FSYNC to SCLK hold time (t8) says the max i can set is 20ns. With the 40MHz setting i am not able to set that value, the minimum i can go is 30ns.

When i key in 20E-9 for the 'SPITimeCS2CLK' property, i gives an value incompatible error with a red highlight. I tried the same configuration when i set the SCLK for the SPIbus with 20Mhz and 60MHz, and i am still getting the same output

[Robin_Shen]

Since AD9833 is not a product of NXP, I am not sure if it is because you did not send these SPI data according to the Command Sequence Explained section of AN-1070. I checked ad9833_init (https://github.com/analogdevicesinc/no-OS/blob/main/drivers/frequency/ad9833/ad9833.c#L128) and it seems that you should follow AN-1070 to send SPI data.
It is recommended to send these SPI data: 0x2100 0x50C7 0x4000 0xC000 0x2000

[soumik1506]

i have attached the new code which is based on the no-os driver.

[Robin_Shen]

The following is the SPI waveform after I debugged the AD9833_TX_SPI of your attached project (SPI_ONLY_M7_0_0):
Since my S32K358 mini has a 16MHz crystal onboard, I modified the clock part, and I also increased the values ​​of SpiTimeClk2Cs and SpiTimeCs2Clk.

I found two problems based on the SPI data on the logic analyzer:
1. 0x0000 is sent extra every time. Why did you #define DAC_STACK (4U)? Shouldn't it be 2U?
2. You called AD9833_TX_SPI(0x2100); but sent 0x0021. It seems that you reversed the higher 8 bits and the lower 8 bits. Please modify the assignment of TxMasterBufferAD3988[0] and TxMasterBufferAD3988[1].

[soumik1506]

Thanks for your reply. I will change the DAC_STACK size and the tx buffer assignment like you pointed.

As per the AD9833 datasheet, the operating frequenct must be up to 40Mhz, what was your LPSPI bus frequency, and what was your SpiTimeClk2Cs and SpiTimeCs2Clk times.

Was your SpiTimeCs2Clk within 20ns?

Can you give the project with your changes

[Robin_Shen]

The serial clock can have a frequency of 40 MHz maximum. 

The maximum frequency mentioned in the AD9833 datasheet does not mean that you must communicate with a 40MHz SPI clock. You can also use a lower SPI clock frequency.
Please note: 

For S32K314, S32K322, S32K324, S32K328, S32K338, S32K341, S32K342, S32K344, S32K348, S32K358, S32K388,S32K396: The maximum baudrate for LPSPI0 is 20MHz, for LPSPI1-LPSPI5 is 10MHz, for FLEXIO is 10MHz.

Also, FreqReg is calculated using MCLK, not SLCK. 

[soumik1506]

Yes i am aware that FreqReg is calculate using the MCLK and the max baudrate for LPSPI2 is 10Mhz.

I am talking about the operating frequency of AD9833 and the serial clock of the LPSPI2 bus. I have tried setting the LPSPI2 bus with frequencies lower than 40Mhz (20Mhz), i am not able to set the SPItimeCs2Clk time within 20ns. The the data that i am trying to send is not setting the FreqReg.

I want to to know what must be clock configuration. Can you please tell me this clearly coz i am pressed with time here!!

[Robin_Shen · Accepted solution]

As the S32 Configuration Tool indicates for SpiTimeClk2Cs and SpiTimeCs2Clk: This parameter allows to use a range of values ​​from 30ns up to 0.01s. So you can't set SPItimeCs2Clk to 20ns.

I don't understand why you have to set SPItimeCs2Clk(t8) to 20ns. As far as I understand, when LPSPI2 operates at 10MHz, the SCLK period(t4) is equal to 100ns. So t8 max=t4-5=100-5=95ns. You just need to set SPItimeCs2Clk(t8) between t8 min and max, which is between 10ns and 95ns.
I just set SpiTimeClk2Cs and SpiTimeCs2Clk to 30ns which is 0.00000003.

AD9833 is not a product of NXP, porting AD9833 - Microcontroller No-OS Driver is out of scope of our online technical support. 

Since you don't use MISO pin, it is recommended to enable SpiHalfDuplexModeSupport and use Lpspi_Ip_SyncTransmitHalfDuplex instead of Lpspi_Ip_SyncTransmit.

I modified Lpspi_Ip_HalfDuplexTransfer_S32K358_RTD400HF02 to send the command initialization sequence '0x2100 0x50C7 0x4000 0xC000 0x2000' from the AN-1070 example. Regarding the control of AN-1070 I suggest you also contact technical support at www.analog.com.