continous reset on RSTB assertion on NXP(S32G399) Pmic-VR5510

[jvs0473]

After PMIC Initialization (VR5510) 

We have observed the fluctuation of RST_B pin in the following scenarios:

i)RSTB_REQ from the PMIC through I2C

ii)on the watchdog maximum error count , configured reaction is fs0b only

ii)OFF MODE REQ from the PMIC through I2C

Can you please help here.

[diazmarin09]

Hello,

I hope all is great with you. Thank you for using the NXP communities.

Do you mean that the RSTB pin is not behaving as expected? Could you please share more details?

1. For example, when the watchdog error counter reaches its maximum value, the Fail-safe reaction on RSTB and/or FS0B is configurable with the WD_FS_IMPACT[1:0] bit field (FS_I_WD_CFG register) during the INIT_FS phase.

How is the WD_FS_IMPACT bit configured?

2. How is your watchdog configured?
3. Could you please share your RSTB pin configuration (schematic)?

Regards,

David

[jvs0473]

Hello,

The above following scenarios has been tested individually.

WD_FS_IMPACT - FS0B only is asserted if WD error counter = WD_ERR_LIMIT[1:0]
 WD_FS_IMPACT - FS0B and RSTB are asserted if WD error counter = WD_ERR_LIMIT[1:0]
In both these cases we observed the same behavior. Reset pin is going to low(0v) and high(3.3v)

2)Watchdog is configured with 12ms window period with DC(68.75%, 31.25%) , Error limit - 8
3)

PMIC 

S32G

B is connected to LDO3_S32G in the below screenshot. 

Please help to analyze why RSTB pin is fluctuating instead of going to Reset

[diazmarin09]

Hello kavya23,

Once again, thank you for using the NXP community.

As we know, the RSTB is an open-drain output that can be connected in the application to the MCU's RESET pin. RSTB requires an external pull-up resistor to VDDIO or VPRE and a filtering capacitor to GND for immunity.

Finally, could you please share the pull-up resistor value on the RSTB pin?

Regards,

David

[jvs0473]

Hello,

Thank You for Replying.

External register of 2K Ohm to VPRE has been provided.

The time between the RSTB pin low and high is 4s approx. which is same as Auto Re-try Timeout set via OTP and hence providing expected behavior.
The issue we are not understanding is why it is going to Deep Fail State after the first Reset. Somehow the RSTB is not released after the Reset REQ from PMIC or from S32G or due to WD error count =WD Error Limit.

[jvs0473]

Hello,

Sorry for the late response.

1. It is reproducible on other boards also.

2.Waveform(screenshot) is attached below. RSTB_DUR bit is configured to 0(10ms)

3. Even though FLT_ERR_IMPACT is configured to No effect on RSTB and FS0B, observed the same behavior on RSTB REQ or OFF Mode Request

[diazmarin09]

Hello jvs0473,

Please review the response from our specialist below:

This is expected behavior.

RSTB and FS0B are both asserted when no watchdog refresh in INIT_FS.

The device will go into Deep-FS mode when fault error count reach to limit=6 default.

Please check the page50 to Page 55 in attached slides, especially page53 for Watchdog operation mechanism.

The WD_INIT_TIMEOUT_OTP in customer OTP was set to 1024ms according to their test waveforms.

Customer needs to refresh the WD before INIT_FS timeout. They can enter debug mode during the develop stage. Please check page26 to page30 for more details of debug mode and Deep-FS mode.

Please review the document that I shared with you (it is confidential). 

Please let me know if there is anything unclear. Thanks.

I hope this information will be useful for you. 

Regards,

David 

[diazmarin09]

Your patience is greatly appreciated.

Please review the response from our specialist below:

1. This behavior can be captured on only one board, or can be reproduced on different board? Can customer try on another board?

2. Can customer show us the waveform of the fluctuation of RST_B pin (instead of reset).   Do they mean they only can see a RSTB low pulse but not RSTB maintaining low?

RSTB is asserted low for about 1ms or 10ms(configurable with RSTB_DUR bit) after RSTB_REQ request or OFF MODE REQ request. It is expected behavior.  

3.For the event of watchdog error, can customer check below register value to see whether the RSTB is asserted due to the Fault Error Counter intermediate value. 

Regards,

David 

[diazmarin09]

Hello jvs0473,

I am pleased to contact you again.

I want you to know that we are working internally on your requested.

We will do our best to get back to you as soon as possible with a resolution to your issue.

I will appreciate your patience and  your understanding.

Regards,

David