Where is the program for initializing the PB_07 pin in the BSP35.0 of S32G274?

[sdx111]

Where is the program for initializing and operating the level of PB_07 pin in the BSP35.0 of S32G274? Where in ATF, Uboot and Linux are there operations related to this pin?sdx111_0-1770628721137.png

[sdx111]

Also, where is the program for initializing the PB_13 pin in the BSP35.0 of the S32G274?
I can't find these in the device tree. Could you please tell me where to look for them or if there are any relevant documents?

[sdx111]

Also, where is the program for initializing the PB_12 pin in the BSP35.0 of the S32G274?

[Joey_z]

Hi,sdx111

Thank you for contacting us.

Why do you want to operate the pin of PB_07/PB_12？ Do you want to operate the pin in the uboot or linux?

BR

Joey

[sdx111]

Because I was adjusting the dual-core boot, the M7 core needed to control these pins, but once the A core started, these pins were modified to a low level by the M7 core. Therefore, I need to remove the program that controls these pins from the A core.

[Joey_z]

Hi,sdx111

Thank you for your reply and information.

Do you use our RDB2 board or customer board? do you have any modify about the .dtsi file in ATF/Kernel?

Please try to check the pin status change, is it status changed in the uboot or kernel boot stage? You can try to test it, because both have the pin initial operation.

1.For the pin PB_12/PB_13, I suspect it is affected by the LPSPI2 or function pin on A core.

2.For the PB_07, do you use the SJA1110 initial on A core? it may impact the pin of PB_07.

BR

Joey

[sdx111]

I am using the RDB2 board. The dtsi file has not been modified yet. It will change during the kernel startup stage.
I know that it is the function pins on the A kernel that have an impact, but I would like to know in which file the initialization and pin operation programs for these specific A kernel pins are located?

[Joey_z]

hi,sdx111

Thank you for your reply.

The PB_07 is connected to the KSZ_A_INT_B, the INT/PME_2 signal is from the PHY of KSZ9031 for GMAC0, you can try to disable the GMAC0 to check this pin status.

BR

Joey

[sdx111]

I need to apply GMAC0 of A kernel. I just want to remove the programs related to PB_07. Could you please clarify which function in which file it is?

[Joey_z]

Hi,sdx111

Thank you for your reply.

PB_07 is used for the KSZ_A_INF_B to connect the PHY, INT/PME_2 is the "Interrupt Output / Wake-up Output (PME)" pin of KSZ9031, the signal is transmitted from PHY to SOC. 

The definition of this pin was not found in the device tree. This might be because the MDIO polling function of the PHY was implemented, the interrupt function of the PHY was not implemented.

Joey_z_2-1770708982073.png

Joey_z_1-1770708739993.png

What state do you want PB_07 to maintain? PB_07 should be set as the input mode for this application. PB_07 is also pulled up by an external pull-up resistor on RDB2. If the signal of the PHY changes, the pin may a state change. It is necessary to refer to the manual of the PHY to get more information about this pin signal. 

BR

Joey

[sdx111]

Could you please take a look at the requirements I mentioned before? It feels like we are always going round and round on this issue. I said that the M7 core needs to use this PB07 pin as an output high level. This is my application scenario. However, when the A core enters the Linux system, the PB07 pin will become a low level. Therefore, I need to delete the program for the PB07 pin of the A core. I also couldn't find the initialization of PB07 in the device tree. If it was used in the MDIO polling, please let me know in which part of the program or which file it was applied. If you guys can't find these internally, then how can the external users use them?

[Joey_z]

hi,sdx111

Thank you for your reply.

M7 core needs to use this PB07 pin as an output high level. This is my application scenario. However, when the A core enters the Linux system, the PB07 pin will become a low level.

>>>Where is your test point? For your testing, dose the "high level" is 3.3V and "low level" is 0V?

is it will still become a low level if you only use the A core?

BR

Joey

[sdx111]

The high level is 3.3V and the low level is 0V. Even if I only use the A core, it will also become the low level.

[Joey_z]

Hi,sdx111

Thank you for your reply and information.

I will help you to check this issue and discuss with internal experts.

Also, I use the RDB2 board and default BSP35 on A core, the pin of PB_07 not change to low level during A core boot, could you send your file of s32g274a-rdb2.dtb to me? I will help you to test it.

BR

Joey

[Joey_z]

Hi,

Also, please share me the file of s32g274a-rdb2.dtb in your folder as the below.
./arch/arm64/boot/dts/freescale/s32g274a-rdb2.dtb

BR

Joey

[sdx111]

Could you please take a screenshot to show me where it is? I actually couldn't find the mentioned "s32g274a-rdb2.dtb" file in this path.

[sdx111]

I didn't find s32g274a-rdb2.dtb under this path.

[Joey_z]

Hi,sdx111

感谢您的回复，为了方便交流，我会使用中文给您回复！

1.我使用默认的BSP35启动A核测试PB_07，没有发现这个管脚被拉低，而是维持在1.7V左右。我已经收到您们的dtsi源文件, 您们做了一些修改，为了排除软件问题，您可以尝试使用默认的BSP35启动A核测试PB_07管脚吗？我的测试点如下图：

Joey_z_2-1770806560951.png

2.在RDB2上，根据您们提供的信息，Kernel启动阶段导致管脚拉低，可能由于软件原因拉低了管脚，另一方面可能由于PB_07和PHY 的INT相连，PHY外部操作了这个管脚。建议优先排除PHY的干扰，由于BSP35版本比较老了，无法直接给您提供修改内容，需要一些时间调查，不排除内核有代码初始化这个pin的原因，希望您的理解。

BR

Joey

[sdx111]

1、因为我还需要调试双核启动的其他东西，所以我用原来的BSP35.0测试可能需要先暂时搁置一下。另外想问一下如何在linux kernel启动后，使用命令来查看PB_07引脚的初始化寄存器？
2、我们是用的我们自己做的板子，PB_07可以说是悬空的，根据RDB2的板子来看这个PB07应该是被用作了EIRQ，应该是被用作了输入的。另外能不能给我一个关于整个系统加载启动的流程说明和源码说明文档，我也可以看看PB07的加载，因为这个工程有的引脚不在设备树初始化，实在不太好找。