When is SSRAM accessible before s32_ssram_clear?

[Jeff-CF-Huang]

Hi Sir,

enum reset_cause {

    CAUSE_POR,

    CAUSE_DESTRUCTIVE_RESET_DURING_RUN,

    CAUSE_DESTRUCTIVE_RESET_DURING_STANDBY,

    CAUSE_FUNCTIONAL_RESET_DURING_RUN,

    CAUSE_FUNCTIONAL_RESET_DURING_STANDBY,

    CAUSE_WAKEUP_DURING_STANDBY,

    CAUSE_ERROR,

    CAUSE_MAX_NUM

};

Which reset reason is SSRAM accessible before s32_ssram_clear function?

Best regards,

Jeff Huang

[alejandro_e]

Hello @Jeff-CF-Huang, 

Checking the reference manual for the registers value for reset (MC_RGM_DES and MC_RGM_DES) which are read in function  static enum reset_cause get_reset_cause(void) [.../arm-trusted-firmware/plat/nxp/s32/s32cc/s32g/s32g_bl2_el3.c][page 1139, S32G2 Reference Manual, Rev. 8, February 2024] (please check the full table in the document for better reference):

I was not able to find any error directly related to the a SSRAM access. Please provide the following information to have better context of your setup:

• Have you experienced problems when accessing the SSRAM before clearing it? 
• Are you using a S32G2 or S32G3?
• Which version of the BSP are you using?
• Are you using a multicore setup? this is M7 and A53 cores
• which boot type are you using? QSPI, SD, eMMC, serial
• Are you using a custom board or a RDB board?
• Are you using the GCC version indicated in your BSP user manual?

Thanks for the information in advance.

[Jeff-CF-Huang]

Hi Alejandro,

It seems there’s a misunderstanding.
The s32_ssram_clear function initializes and clears the SSRAM in BL2 of ATF.
If we want to retrieve data from SSRAM after an XXX reboot, we need to access SSRAM before this function is called.
However, we are unsure which type of reboot allows SSRAM to be safely read.
From what we know, reading SSRAM before s32_ssram_clear during a POR scenario results in a system fault.

Best regards,
Jeff Huang

[alejandro_e · Accepted solution]

Hello @Jeff-CF-Huang,

Thanks for the clarification, I did understand the question differently.

To know when exactly the SSRAM content is retained please check the section 28.7 Chip status on reset exit of the Reference manual [page 1150, S32G2 Reference Manual, Rev. 8, February 2024]:

Please check the reference manual for full information.

In the table I mentioned before you can see the resets that are of type functional:

About the status of the SSRAM you can check the 35.3.5 Platform RAM Status Register (PRAMSR) register to know if it was successfully initialized and therefore can be accessed [page 1436, S32G2 Reference Manual, Rev. 8, February 2024]:

You can learn more about how to initialize the SSRAM in section 35.1.4 Initialization, under Chapter 35 SRAM Controller (SRAMC) [page 1427, S32G2 Reference Manual, Rev. 8, February 2024]:

My understanding is that with a functional reset (this is when the information is retained) the SSRAM should not loose the initialization status and therefore you should be able to read it without problems. Please note that the SSRAM depends on the STANDBY power domain (VDD_IO_STBY), so that voltage needs to be kept in order to retain the SSRAM data.

I used the S32G2 RM as reference since I do not know which component you are using.

Let me know if this information solved your question.