What does PFE HIF_SOFT_RESET need on S32G399A-RDB3

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What does PFE HIF_SOFT_RESET need on S32G399A-RDB3

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ghs_khuang
Contributor I

(We are using our own operating system, not Linux)

We ported PFE FW 0.9.X like two years ago and it works fine on RDB2. But it seems not support S32G3. So I downloaded the latest s32g_pfe_*.fw file from version 1.5. But HIF initialization fails because of this “reset timed out” in pfeng_hw.c:

/* SOFT RESET */
writel(HIF_SOFT_RESET_CMD, base + HIF_SOFT_RESET);
while (readl(base + HIF_SOFT_RESET) & ~CSR_SW_RESET) {
if (++ii < 1000u) {
        mdelay(1);
} else {
pr_err("HIF reset timed out.\n");
return -ETIMEDOUT;
}
}

I’ve configured the SIUL2, CGM, and clock of PFE-MAC2 (I don’t care about PFE-MAC0 and PFE-MAC1 for now. I just want PFE-MAC2 run on RGMII mode) and I don’t know what else I missed. My questions are:

  1. What does HIF SOFT RESET require for it to succeed?
  2. Do I have to configure the PFE-MAC0 and PFE-MAC1 as well even if they are not used?
  3. Although the fw file is the latest, I’m still using our two-year-old PFE code to load it because the new ones in release/bsp35.0 is quite different and will need a lot of time to port to our RTOS. I’ve ported everything under the “on_g3” flag in the pfeng_hw.c. Is it OK?
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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

S32G3 information is still under distribution control. Help us opening a ticket inside the NXP online service or contacting your local NXP representative/FAE, for them to channel it through the correct medium.

We do apologize for this inconvenience.

Please, let us know.

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