Update IVT in RAM failed?

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Update IVT in RAM failed?

741 Views
bookar
Contributor II

I am working on S32G m7 core, with S32DS。 

to satrtup from SD card, I modified the .ld file acording to <S32G-GOLDBOX-SW-UG> page 19, and then I found that the uart interrupt handler dont sevice correctly。

It seem's that the IntCtrl_Ip_InstallHandler interface dont install the handler correctly, and the default undefined_handler will be called, instead of the expected handler that installed by IntCtrl_Ip_InstallHandler。

Is that caused by cache? 

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6 Replies

723 Views
Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi, 

Could you provide us with what S32DS/RTD version you are working with? Also, are you working with any NXP board?

Following the S32G-GOLDBOX-SW-UG, did you create the example it is provided in there? Did it work?

Have you tried with other examples? The behavior is the same?

Please, let us know.

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717 Views
bookar
Contributor II

Hi,

Thanks for your reply.

I,m working on GoldBOX, with S32DS version 3.4, RTD  version 3.0.2, and SPD version 1.9.0。

I didnt try other project with this ld file, I will try later.

Forgot to mention, with the "int_sram_no_cacheable" area start from 0x34500000 in ld file, everything seem,s to be OK。

 

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707 Views
Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Thanks for your feedback.

Just to verify, if "int_sram_no_cachable" is set as the default (ORIGIN=0x35000000, LENGTH=00100000), you see no problem?

Please, let us know.

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699 Views
bookar
Contributor II

yes.

if "int_sram_no_cachable" is set as the default (ORIGIN=0x35000000, LENGTH=00100000), there is no problem。the uart interrupt handler installed with IntCtrl_Ip_InstallHandler works well。

 

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692 Views
bookar
Contributor II

Correction: The default of "int_sram_no_cachable" is (ORIGIN=0x34500000, LENGTH=00100000)。

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678 Views
Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Thanks for the correction. We were wrong in the value, as you noted.

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