Dear NXP Community,
I have questions regarding the Ethernet communication capabilities of the S32G chipset:
1. Inter-Core Ethernet Communication
- Is it possible to establish Ethernet communication between the Cortex-A and Cortex-M cores within the S32G3 chipset?
- If possible, what is the recommended configuration/setup for this internal communication?
2. Ethernet Addressing
- Can each core (Cortex-A and Cortex-M) be assigned its own unique Ethernet address?
- If yes, how are the MAC addresses managed between the cores?
Any documentation or example configurations would be greatly appreciated.
Thank you in advance for your help.