Subject: S32G3 Internal Ethernet Communication Between Cortex-A and Cortex-M Cores

[dylee]

Dear NXP Community,

I have questions regarding the Ethernet communication capabilities of the S32G chipset:

1. Inter-Core Ethernet Communication
- Is it possible to establish Ethernet communication between the Cortex-A and Cortex-M cores within the S32G3 chipset?
- If possible, what is the recommended configuration/setup for this internal communication?

2. Ethernet Addressing
- Can each core (Cortex-A and Cortex-M) be assigned its own unique Ethernet address?
- If yes, how are the MAC addresses managed between the cores?

Any documentation or example configurations would be greatly appreciated.

Thank you in advance for your help.

[chenyin_h]

Hello, @dylee 

Thanks for your post.

From my understanding, I suggest using the PFE master, PFE slave to establish Ethernet communication between the Cortex-A and Cortex-M cores, for the configuration, it could be the M core master and A core slave, or vise-versa.

I suggest reading the chapter7 of BSP UM and User Manual for S32G PFE MCAL 4.4 Driver for further information on this feature.

BR

Chenyin