SPI BUS DISCUSSION about SPI frame interval time

[db16122]

Hi NXP colleague，

For SPI performance about S32G, there are some notes need to check.
We are using the SDSPI interface to connect with S32G that means crypto IC has SD interface and we are using 4 line SD protocol mode to connect as SPI bus.
That can explain why the transfer rate is relatively low but we already hardly work with CONTI for a month to improve the effiency from LINUX kernal level.
So from software driver side, the seems there are not too much we can improve and we already use interrupt mode ：（

For hardware side, usually there are interval between each clock cycle, it may be config to reduce if replace from CS/GPIO to PCS.
So if SPI config can be used to improve the gap between each data cycle, it will be much helpful. ：）

[db16122]

Understand, is it possible to control CS to be deasserted at each SPI frame? by hardware PCS control or by internal high level linux high level software setting?

[Daniel-Aguirre]

Hi,

At this moment, the "Spi_Ip_Transfer_S32G274A_M7" project provided in the RTD for S32G2/3 is doing the deassert of the CS on each SPI Frame (8 bits, as configured in the project).

This should give the start point on trying to reduce the interval between frames, to see if you can find a feasible time for your specific application.

Please, let us know if this information was helpful or not.

[db16122]

how about the time interval between different time frame besides CS2CS?

We need to config the setting to reduce the time between each time frame. Is it possible to reduce them with PCS?

Right now the setting include CS2CS, CLK2CS, CS2CLK, but how about CLK2CLK?

[Daniel-Aguirre]

Hi,

At this moment, the S32G platform does not have a register to modify what you are suggesting for a CLK2CLK parameter. So, this is not feasible under the current platform architecture.

The suggestion for lowering CS2CS we gave it is because we saw a decrease in the period between each SPI transfer.

For our example, CS is being deasserted on each transaction, that is why we are seeing this. For your example, we are seeing that on each transaction, CS is not being deasserted, but the period seems to be dictated by the same CS2CS/CLK2CS/CS2CLK parameters.

Please, let us know if this information was helpful or not.

[Daniel-Aguirre]

Hi,

Are you using S32DS for this application? If so, inside the "Peripherals" ConfigTools will be the Spi_Ip_n module. Within SpiDriver tab (inside Spi_Ip_n module) will be an option called "SpiTimeCs2Cs" in which defines the width of the CS pulse (when idle). You can try and lower this time to your needs (and inside the specs defined in the S32G datasheet). For my case, it helped reduce the interval between one transaction and another.

Please, let us know if this information helps yo or not.