S32G399A STM issue

[asj]

Hi everyone,

I'm facing an issue with the STM1 timer. I've configured two counters: Counter_1 running at 1ms for STM0 (CH0) and Counter_2 running at 1us for STM1 (CH0). The STM0 counter works fine, but STM1 is not updating as expected. Instead of updating every 1us, it updates every 15-25s. 

Configuration Details:

Clock for both STM0 and STM1: 133.33333 MHz
Prescaler (PSC) for both: 1
Compare values: 0x208D5 for 1ms (STM0) and 0x85 for 1us (STM1)
Interrupt priority: 4 for STM0, 5 for STM1

[asj]

These are my ISRs where I set the CMP value by adding a "timeout value" (0x85 for 1us), and clear the interrupt flag, these are done inside "Handler":

ISR(IsrSTM0)

{

    Handler((uint8) STM_CFG_STM0_INSTANCE, (uint8) STM_CFG_STMN_CH0);

    Os_IncrementCounter_Counter_1();       

}

ISR(IsrSTM1)

{

    Handler((uint8) STM_CFG_STM1_INSTANCE, (uint8) STM_CFG_STMN_CH0);

    Os_IncrementCounter_Counter_2();

}

[Joey_z]

Hi，asj

Thank you for contacting us.

Could you share more information about your code? For example, how do you configure your STM?

In addition, is it normal only to use the STM1?

BR

Joey

[asj]

This is my STM configuration:

static const Stm_Prv_InstanceConfig_tst Stm_Cfg_PbInstanceConfInirba_Stm_Config_acst[STM_CFG_PB_NUMBER_OF_STM_INSTANCES] =
{
/* STM peripheral instance*/ /* Freeze mode */ /* Prescaler value(range 1 to 256) */

/* Instance configuration for instance STM0*/
{
STM_CFG_STM0_INSTANCE, // STM peripheral instance
TRUE, // Freeze mode
1, // Prescale value(range 1 to 256)
},
/* Instance configuration for instance STM1*/
{
STM_CFG_STM1_INSTANCE, // STM peripheral instance
TRUE, // Freeze mode
1, // Prescale value(range 1 to 256)
},

};

static const Stm_GptChannelConfig_tst Stm_Cfg_GptPbChannelConfigInirba_Stm_Config_acst[STM_CFG_GPT_NUMBER_OF_LOGIC_STM_CHANNELS] =
{
/* Instance of the STM STM hardware channel */
/* peripheral, STM_REG_STMN_CHm */
/* m = 0, 1, 2, 3
{
STM_CFG_STM0_INSTANCE,
STM_CFG_STMN_CH0,
},
{
STM_CFG_STM1_INSTANCE,
STM_CFG_STMN_CH0,
},

};

This is how I'm setting the compare value:
Stm_StartTimer((uint8)  RBA_STM_CFG_STM0_INSTANCE,

                          (uint8)  RBA_STM_CFG_STMN_CH0,

                          (uint32) 0x208D5);                   // 1ms

    //Rework OS timer clock value

    // Init OS system timer - STM1 and CH0

Stm_StartTimer((uint8)  RBA_STM_CFG_STM1_INSTANCE,

                         (uint8)  RBA_STM_CFG_STMN_CH0,

                          (uint32) 0x85);                   // 1us

Stm_StartTimer function does the following:

/* Read the current counter value */

     Stm_Prv_CounterStartValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]= STM_PRV_REG_CNT((HwTimerInstance_u8));

     /* Load the compare value,which is the sum of current counter value and timeout value */

     STM_PRV_REG_CMP((HwTimerInstance_u8), (HwTimerChannel_u8)) = (uint32)(TimeOutValue_u32+Stm_Prv_CounterStartValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]);

     /* Store the timeout value */

     Stm_Prv_TimeoutValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]=TimeOutValue_u32;

     /* Enable the channel */

     STM_PRV_REG_STMCCR_CEN_TIMER_CH_ENABLED((HwTimerInstance_u8), (HwTimerChannel_u8));

The logic for updation of CMP value:

/* store current compare value */

    Stm_cmp_value_u32=STM_PRV_REG_CMP((HwTimerInstance_u8), (HwTimerChannel_u8));

    /* Set the compare value */

    STM_PRV_REG_CMP((HwTimerInstance_u8), (HwTimerChannel_u8))=(uint32)(Stm_cmp_value_u32 + Stm_Prv_TimeoutValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]);

}

And as for the second question, I'm trying to use both STM0 and STM1 for different time intervals, to implement counters for my usecase.

[Joey_z]

hi,asj

Thank you for your information.

I will try to look at the code for you and find the problem. In addition, The second problem is that I suggest that you do not apply STM0 and only use STM1 to check whether STM1 itself is configured incorrectly. If STM1 works well alone, you should focus on finding configuration problems between the two STMS when they are used.

BR

Joey

[asj]

Okay, I can do that, but the thing is if I'm using them both for 1ms, they work. So that's why I had the doubt. Anyways, I'll do it and let you know

Do let me know if you find anything from the code

[Joey_z]

hi,asj

Are you using STM0 and STM1 in debug mode, and if so, check to see if the value of CNT reaches the comparison value to enter the interrupt.
Also, try setting Freeze mode to FALSE.

BR

Joey

[asj]

Hi Joey,

Yes, I am. The CNT value for STM0 (1ms) continuously updates every 1ms, upon reaching CMP value (IRQ assertion is happening properly). But for STM1 (1us), the CMP value only updates after CNT value falls over from FFFFFFFF to 00000000 and then matches the CMP value (IRQ assertion is improper). So, it takes 10-15s for my counter to update its value.

Thanks,

asj

[Joey_z]

hi,asj

Sorry for replying so late.

Did you try setting Freeze mode to FALSE?

Additionally, after the channel interrupt has been handled, clear the channel interrupt flag (CIF).

BR

Joey

[asj]

Hi Joey,

Sorry for the late reply.

Yes, I'm doing that. My doubt now, is whether a time period of 1us is feasible. This means 1000000 interrupts per second. So, it might lead to a runtime problem. Could you shed some light on this?

BR

asj

[Joey_z · Accepted solution]

hi,asj

Thank you for your reply.

According to the timer's PSC and clock frequency, it is theoretically possible to achieve 1us, if you doubt the reason for performance, you can try to set STM1 larger time, such as 100us or 2ms.

BR

Joey