S32G399 PCIe cannot send TLP packets

[LONGGANGSU]

As shown in the figure, please help me. Currently, I am using the S32G399A chip and connecting it to an FPGA via the PCIe interface. In this configuration, the S32G399A acts as the RC and the FPGA acts as the EP. The problem I am encountering now is that the config space of the FPGA can be accessed, but the mem space of bar0 cannot trigger TLP.
The following figure shows the information printed by "dmesg" in the operating system. In the "outbound" section, it shows 6OB and 4IB. How should this outbound and inbound be configured and where should it be configured?

Also, what do Original Address  Base Address  Target Address represent respectively?

[chenyin_h]

Hello, @LONGGANGSU 

Yes, from the test, under current BSP driver, the RC would automatically map the region to 32bits/64bits address space according to the BAR settings from the EP.

BR

Chenyin 

[chenyin_h]

Hello, @LONGGANGSU

Let me continue supporting it here.

From the log shown, there are 6OB windows and 4 IB windows.

1. The number of OB windows and IB windows would often depend on the HW IP, do you think the number of them are enough for you or not? for configure the iatu, you may check the driver under drivers/pci/controller/dwc for your settings.

2.  The Original address could be the address in the request from memory domain, the base Address could be the reference point for the region in the host address space, while target address is the starting point in the PCIe domain.

BR

Chenyin

[LONGGANGSU]

May I ask, how can I configure the PCIe RC mode to be 64-bit wide?

Currently, I am communicating with the FPGA using a 32-bit width.

[chenyin_h]

Hello, @LONGGANGSU 

Thanks for your reply.

The S32G PCIe RC supports 64bits address access

For example, I used another S32G board as EP,  modified the corresponding bits for BAR on EP side, then after booting the RC, from the output from RC side, one region mapped is "Region 0: Memory at 4900000000 (64-bit, prefetchable) [size=1M]", it could be accessed via 64bits address.

You may check your own PCIe EP drivers/RM for detailed modification method.

BR

Chenyin

[LONGGANGSU]

Do you mean that the PCIe bit width is related to the EP? If the EP end is 64 bits, then is there no need to make any modifications to the RC end?

[chenyin_h]

Hello, @LONGGANGSU 
Thanks for the reply.

I found this issue is also introduced via other channel, help it there directly.

BR

Chenyin 

[LONGGANGSU]

Does it mean to solve it through FAE?@cehnyin_h

[chenyin_h]

Hello, @LONGGANGSU 

Thanks for the post.

1. Seems you are working with BSP, which version?

2. Which serdes is used for connected to the device, PCIe x1 is used?

3. For the snapshot mentioned, which document it referred to?

BR

Chenyin 

[LONGGANGSU]

1.BSP是43.0

2.是pcie X1。

3.第二张照片是RMS32G3SERDES.pdf，3.10.3章节。