S32G3 remoteproc support

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S32G3 remoteproc support

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Niranj_369
Contributor I

Dear NXP Team,

I’m currently working with the S32G3 SoC and exploring parallel booting of the A53 and M7 cores, based on the guidelines provided in the AN13750 application note. I understand that this document is intended for the S32G2 platform.


1.  Is there an equivalent or updated document specifically tailored for the S32G3 SoC that covers parallel booting?
2. Can I use remoteproc on the A53 core to load firmware onto the M7 core? If so, does this setup support IPCF or any other inter-core communication mechanisms? I would appreciate any documentation or references that detail this process for S32G3.

 


Thank you for your support.

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Joey_z
NXP Employee
NXP Employee

hi,Niranj_369

Thank you for contacting us.

1.We do not have the newer version of AN13750, you also can refer to the AN13750 for your S32G3 platform, the steps are similar。

2.You can refer to the demo of IPCF in RTD, and you can try to test how to load the IPCF sample from u-boot.

Joey_z_0-1760062037621.pngJoey_z_0-1760062037621.png

Hope this can help you.

BR

Joey

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8,785 Views
Niranj_369
Contributor I

Hi @Joey_z 
1. In step 7, how can i find the address of the address of the interrupt vector.
2. After executing these commands, if i execute boot commands, will both the cores are active?
3. Is there any simple example for m7  that i can try to check if it works(ie M7 fIrmware boot)?. Currently im using the IPCF M7  firmware. but im facing some issues while enabling IPCF in A53 core. 
4. For enabling IPCF in A53 core, is the ipc-shm drivers only enough or i need dtb changes or other changes
ipc-shm-dev.ko, ipc-shm-uio.ko. ipc-shm-multiinstance.ko - do i need to insmod all these drivers?
Im getting the below error while insmoding ipc-shm-multiinstance.ko


root@s32g399ardb3:~# sudo insmod files/ipc-shm-sample_multi-instance.ko
[ 55.467428] SError Interrupt on CPU2, code 0x00000000bf000002 -- SError
[ 55.467449] CPU: 2 PID: 590 Comm: insmod Tainted: G W O 6.6.52-rt43-g1a29a32be610-dirty #1
[ 55.467458] Hardware name: LUCID NXP S32G3 Design Board (S32G-VNP-RDB3) (DT)
[ 55.467462] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 55.467470] pc : ipc_shm_init+0x238/0x8cc [ipc_shm_dev]
[ 55.467492] lr : ipc_shm_init+0x124/0x8cc [ipc_shm_dev]
[ 55.467506] sp : ffffffc081e738f0
[ 55.467509] x29: ffffffc081e738f0 x28: ffffffc078f46068 x27: 0000000000000000
[ 55.467521] x26: 0000000000000000 x25: ffffffc078f3d490 x24: ffffffc078f3d480
[ 55.467532] x23: ffffffc080eeef40 x22: 0000000000000000 x21: ffffffc078f46190
[ 55.467542] x20: ffffffc078f3d480 x19: ffffffc078f3d480 x18: ffffffffffffffff
[ 55.467554] x17: 0000000000000003 x16: ffffffc080a4d9a0 x15: ffffffc101e7377d
[ 55.467565] x14: 0000000000000001 x13: 007473696c5f7974 x12: ffffff8801093f1c
[ 55.467574] x11: 000000000000004b x10: ffffffc080a4d9a0 x9 : 0000000000000000
[ 55.467583] x8 : ffffff880613ca80 x7 : 0000000000000000 x6 : 0000000000000000
[ 55.467594] x5 : ffffff880613c988 x4 : ffffff880613c748 x3 : 0000000000000000
[ 55.467604] x2 : 0000000000000003 x1 : 0000000000000000 x0 : 0000000000000048
[ 55.467616] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 55.467620] SMP: stopping secondary CPUs
[ 55.467629] Kernel Offset: disabled
[ 55.467632] CPU features: 0x1,00000008,00020000,1000420b
[ 55.467638] Memory Limit: none
[ 55.604282] ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---

 


note: Im using the yocto from nxp github page with 6.6 kernel version

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8,712 Views
Joey_z
NXP Employee
NXP Employee

hi,Niranj_369

Thank you for your reply.

1. In step 7, how can i find the address of the address of the interrupt vector.

>>>You need to find it in .map file as the following picture.

Joey_z_0-1760497253973.pngJoey_z_0-1760497253973.png

Joey_z_1-1760497396594.pngJoey_z_1-1760497396594.png

2. After executing these commands, if i execute boot commands, will both the cores are active?

>>>Yes,you can boot M core in uboot.
3. Is there any simple example for m7  that i can try to check if it works(ie M7 fIrmware boot)?. Currently im using the IPCF M7  firmware. but im facing some issues while enabling IPCF in A53 core. 

>>>You can try to add the operation of LED/register/Uart in M7 project and check the M7 status.
4. For enabling IPCF in A53 core, is the ipc-shm drivers only enough or i need dtb changes or other changes
ipc-shm-dev.ko, ipc-shm-uio.ko. ipc-shm-multiinstance.ko - do i need to insmod all these drivers?
Im getting the below error while insmoding ipc-shm-multiinstance.ko

>>> You can refer to the file of description file to add .ko files.  The .dtb/Image files need to compatible with IPCF.

Hope this can help you.

BR

Joey

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8,701 Views
Niranj_369
Contributor I

Thanks @Joey_z 

I have loaded the m7 firmware using the provided steps. but the expected functionality is not working. I have converted the elf file to bin file using the cross-compiler objectcopy command. the bin file is not genereted when building the project in s32ds
1. How can i configure the s32ds to generate bin file. 
2. will the elf-bin conversion using  arm-none-eabi-objcopy -O binaryu ${ProjName}.elf ${ProjName}.bin command works?

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8,688 Views
Joey_z
NXP Employee
NXP Employee

hi,Niranj_369

You can configure the S32DS IDE to create the .bin file.

1. Properties->Settings->Cross Settings->Check the Create flash image -> Apply and Close

Joey_z_0-1760521674165.pngJoey_z_0-1760521674165.png

2.General->Check the Raw binary, then rebuild the project, you can find the .bin file in folder of Debug_RAM.

Joey_z_1-1760521684016.pngJoey_z_1-1760521684016.png

Hope this can help you.

BR

Joey

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8,665 Views
Niranj_369
Contributor I

Thanks @Joey_z

I’ve built the binary file for the LED toggling example and loaded it using the provided commands, but the LED isn’t blinking. I’ve verified the LED firmware (ELF) using the Lauterbach debugger.
I used the following commands:

dcache off
mw.q 0x34000000 0x0 0x40000
fatload mmc 0:4 0x80000000 led_toggle.bin
cp.b 0x80000000 0x34000000 0x300000
start 0x34501000

The interrupt vector address was taken from the map file

The SRAM range is from 0x34000000 to 0x344FFFFF (5 MiB total).

The binary size is 5.5 MiB (5505024 bytes), which exceeds the available SRAM.

 

If I use 0x300000 (3 MiB) in the cp.b command, it executes without error, but the LED still doesn’t blink. If I use the full binary size (0x5505024), the board resets with the following error:

 

cp.b 0x80000000 0x34300000 0x5505024
"Error" handler, esr 0xbf000000
elr: 00000000ff91d9a4 lr : 00000000ff8b0584 (reloc)
elr: 00000000ff91d9a4 lr : 00000000ff8b0584
x0 : 0000000034300000 x1 : 0000000080000000
x2 : 0000000005505024 x3 : 0000000001100008
x4 : 0000000000000000 x5 : 0000000000000000
x6 : 00000000ff92cb4b x7 : 0000000000000044
x8 : 0000000000000010 x9 : 0000000000000008
x10: 0000000000000004 x11: 00000000ffc0c0d0
x12: 0000000000000000 x13: 0000000000000200
x14: 000000000000000a x15: 0000000000000020
x16: 00000000ff8b04f0 x17: 0000000000000000
x18: 00000000ffbddd80 x19: 0000000000000001
x20: 00000000ffc06ed0 x21: 0000000034300000
x22: 0000000080000000 x23: 0000000000000000
x24: 0000000000000000 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 00000000ffc10cd0 x29: 00000000ffbd4060

Code: eb03005f 540001e1 d65f03c0 f8636824 (f8236804)
Resetting CPU ...

My Questions:

  1. Are these loading steps valid for any M7 firmware, or only for IPCF examples?
  2. Can I reduce the size of the .bin file, or is there another recommended approach to fit it within the M7_0 SRAM range? or is there any other way to overcome this?

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8,614 Views
Joey_z
NXP Employee
NXP Employee

hi,Niranj_369

Thank you for your reply.

1.Are these loading steps valid for any M7 firmware, or only for IPCF examples?

>>>Other M7 Image also can be loaded through these steps. But you need to solve the conflict between A and M core, including clock and pin etc.

Also, do you can test the M7 Image only on M7 core? is the LED will blink?

2.Can I reduce the size of the .bin file, or is there another recommended approach to fit it within the M7_0 SRAM range? or is there any other way to overcome this?

>>> You can modify the link file for this as the following picture.

Joey_z_0-1760581801051.pngJoey_z_0-1760581801051.png

Hope this can help you.

BR

Joey

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8,563 Views
Niranj_369
Contributor I

I'm using a sequence of U-Boot commands to load the M7 firmware on the S32G3 platform. All commands execute successfully, but the expected functionality—LED blinking—is not working.

dcache off
mw.q 0x34100000 0x0 0x40000
fatload mmc 0:4 0x80000000 led.bin
cp.b 0x80000000 0x34350010 0x300000
startm7 0x34451000

QN 1:where can i find the correct load address used in the memory copy command. Specifically, I need clarity on the address and size parameters, what each represents, and where to obtain them. My goal is to boot the M7_0 core of the S32G3 device. Attached the firmware files for reference.

QN 2:I’d like to know whether it's possible to load an ELF file directly from U-Boot. If so, I need the exact commands and guidance on how to determine the correct memory address to use.

Qn 3: I attempted to load the ELF file using the bootelf command, but it resulted in an exception error. I want to understand why this happens and what causes the failure.


=> bootelf 0x80000000
"Error" handler, esr 0xbf000002
elr: 00000000ff91fbc8 lr : 00000000ff91fbc4 (reloc)
elr: 00000000ff91fbc8 lr : 00000000ff91fbc4

QN4: readelf -h led.elf that the class is ELF32. is it expected. is the the reason for the bootelf failure?

image (2).pngimage (2).png
QN5: When I load the LED blinking ELF file using Lauterbach, it works correctly. However, when I try to load the corresponding binary instead, it fails with an unknown symbol error. I need to know what address should be used when loading the .bin file in the Lauterbach CMM script.

Screenshot2.pngScreenshot2.pngScreenshot3.pngScreenshot3.png
QN6: I have used the linker script modification provided to reduce the size of the bin file. will it affect the functionality of the bin file?

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8,537 Views
Joey_z
NXP Employee
NXP Employee

hi,Niranj_369

Thank you for your reply and informaiton.

I will help you to check it and reply to you as soon as possible.

BR

Joey

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8,511 Views
Niranj_369
Contributor I

Thanks @Joey_z 
Im able to boot the M7 core. The error is the wrong load address.

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7,272 Views
arun_belamge
Contributor III
Hello @Niranj_369.
Can you please tell me how did you run the example program on M7 using u-boot?
I have the binary ready with start address 0x34000000 and entry point 0x34500400, but i am not able to run it using startm7.

Thank you!
BR
Arun
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Joey_z
NXP Employee
NXP Employee

hi,arun_belamge

You can post a new ticket for this your question; we will help you to check it.

BR

Joey

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8,354 Views
Joey_z
NXP Employee
NXP Employee

hi,Niranj_369

Thank you for sharing the information.

BR

Joey

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8,327 Views
Niranj_369
Contributor I

We are currently using the BSP 43.0 branch of the auto_yocto_bsp. The M7 IPCF firmware I'm working with — SW32G_IPCF_4.6.0_D2205_updatesite.zip — appears to be incompatible with BSP 43.0. The latest IPCF updatesite I could locate is SW32G_IPCF_4.10.0_Safety_Package_D2405.zip, which officially supports BSP 40.0.

Q1: Does the D2405 updatesite also support BSP 43.0? If not, could you please guide me to the correct IPCF updatesite version compatible with BSP 43.0?

Q2: Which branch of the ipc-shm drivers is recommended for use with BSP 43.0?

Thanks in advance for your support

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Joey_z
NXP Employee
NXP Employee

hi,Niranj_369

Thank you for your reply.

There is no IPCF version corresponding to BSP43 for the time being. It is recommended to use the latest IPCF 4.10.0 version.

BR

Joey

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8,228 Views
Niranj_369
Contributor I

Thanks @Joey_z 

I have built the 4.10.0 M7 IPCF application and attempted to boot both cores by halting at the A53's U-Boot, loading the M7 firmware into SRAM, starting it, and then proceeding to boot the A53 core. However, when the M7 firmware is loaded prior to booting the A53, the boot process halts midway. The attached image compares the A53 boot logs: the left side shows the log with M7 firmware loaded, where the boot fails, and the right side shows the successful boot when the M7 firmware is not loaded.
Note: This only happens with IPCF example. I have successfully done parallel booting with led and lin m7 firmware examples.

Niranj_369_1-1761057401567.pngNiranj_369_1-1761057401567.png

 

To isolate the issue, I commented out all logic in the M7 firmware's main function, yet the A53 still fails to boot completely. Could you please help explain the root cause of this behavior and suggest how to resolve it?

Additionally, I attempted to insert the IPC shared memory drivers (ipc-shm-dev.ko and ipc-shm-sample_multi-instance.ko) while the M7 firmware was not loaded. Inserting ipc-shm-sample_multi-instance.ko resulted in an error. Is this failure due to the absence of the M7 firmware? If not, could you please clarify the cause and advise on how to fix it?

Niranj_369_2-1761057440992.pngNiranj_369_2-1761057440992.png

Note : Im using bsp43.0 with kernel version 6.6. IPCF upfdatesite version 4.10.0 and ipc-shm version 4.10.0.

 

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Joey_z
NXP Employee
NXP Employee

hi,Niranj_369

Thank you for your reply and information.

What is your M7 core IPCF application in RTD? Which version of RTD are you using in RTD?

Please check your M core application linker file and Share Memory, it does not conflict with your A core.

BR

Joey

 

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8,187 Views
Niranj_369
Contributor I

Thanks @Joey_z ,

I’ve followed the steps outlined in the AN13750 document to generate the M7 core IPCF application using:
• RTD version: 4.0.2
• IPCF update site: SW32G_IPCF_4.10.0_DS_updatesite_D2405
Could you please confirm if there are any compatibility issues with RTD 4.0.2? If so, kindly suggest the recommended RTD version for BSP 43.0 and IPCF 4.10.0.
I’ll compare the linker scripts from the working and non-working firmware examples and share my findings shortly

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Joey_z
NXP Employee
NXP Employee

hi,Niranj_369

Thank you for your reply.

Refer to the Release Note of IPCF 4.10.0, the RTD 4.0.2_P04 D2312 is recommended for your application.

BR

Joey

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8,162 Views
Niranj_369
Contributor I

Thanks @Joey_z 

The issue was due to the linker configuration. Initially, I used a linker script that split the SRAM across three cores. Later, I switched to the IPCF example configuration, which allocates the entire SRAM to a single M7 core. With that change, I'm now able to boot the A53 core after loading the M7 firmware — enabling parallel boot.

After that, I tried loading the IPCF drivers on the A53 side by following the steps from the S32DS M7 IPCF example documentation.

Niranj_369_0-1761130177035.pngNiranj_369_0-1761130177035.png

 

The ipc-shm-dev.ko module loads successfully, though it logs the expected warning:

[ 42.983443] ipc_shm_dev: loading out-of-tree module taints kernel.

However, when I try to load ipc-shm-sample.ko, it fails with a synchronous external abort.

Niranj_369_1-1761130348543.pngNiranj_369_1-1761130348543.png

For reference, I built the drivers from the SW32G_IPCF_4.10.0_D2405 branch against our current kernel version (6.6), and the M7 core is running IPCF firmware version 4.10.0.

Could you please help me identify what might be causing the crash or suggest a fix?

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