S32G3 M7

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S32G3 M7

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liujian_abup
Contributor I

At present, the S32G399A development board is used in the project to develop code in the M7 core, and the s19 file compiled by M7 is stored in the SD card, which partition does it need to be placed? How to automatically start the corresponding code in u-boot.

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chenyin_h
NXP Employee
NXP Employee

Hello, @liujian_abup 

I feel sorry that what I posted is just to show an example, not reproducible commands, the M7 binary should be copied to the SRAM before starting it.

To be more detail, let me take IPCF example here for instance:

  1. dcache off
  2. mw.q 0x34100000 0x0 0x40000 //zero the SRAM
  3. fatload mmc 0:1 0x80000000 M7test.bin   //load M7 binary
  4. cp.b 0x80000000 0x34300000 0x300000   //copy it the SRAM(according to the M7 linker file)
  5. startm7 0x34500400 //start it on M7, according to map address

In your actual case, since the loading address and the vector address may vary, the corresponding address should be changed separately.

By the way, there may be issues when running M7 application via u-boot due possible conflicts, a preferred way for running the A53 and M7 tasks simultaneously is to load them via seperate bootloader.

 

BR

Chenyin

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chenyin_h
NXP Employee
NXP Employee

Hello, @liujian_abup 

I feel sorry that what I posted is just to show an example, not reproducible commands, the M7 binary should be copied to the SRAM before starting it.

To be more detail, let me take IPCF example here for instance:

  1. dcache off
  2. mw.q 0x34100000 0x0 0x40000 //zero the SRAM
  3. fatload mmc 0:1 0x80000000 M7test.bin   //load M7 binary
  4. cp.b 0x80000000 0x34300000 0x300000   //copy it the SRAM(according to the M7 linker file)
  5. startm7 0x34500400 //start it on M7, according to map address

In your actual case, since the loading address and the vector address may vary, the corresponding address should be changed separately.

By the way, there may be issues when running M7 application via u-boot due possible conflicts, a preferred way for running the A53 and M7 tasks simultaneously is to load them via seperate bootloader.

 

BR

Chenyin

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liujian_abup
Contributor I

hi,Chenyin:
       Thank you for your reply above, the debugging is now successful。

 

       You described above that a separate boot program is needed to load the corresponding A4 and M7 cores. I see that some introductions need to use EB Tresos Studio configuration tool for debugging, and the official website is all related to autosar. Can we build this boot program by ourselves? The corresponding configuration tool is not used。

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chenyin_h
NXP Employee
NXP Employee

Hello, @liujian_abup 

Thanks for your post.

I assume that you want to load image for M7 side from u-boot prompt, is it right? from my understanding, you may put it on any partition of the SD card, since it would be loaded from SD to the local DDR.

If you want to automatically run it from u-boot, a possible way is to create a command under u-boot prompt, for example, "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};startm7 ${loadaddr}"

 

BR

Chenyin

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liujian_abup
Contributor I
fatload mmc 0:2 0x80000000 M7_code.bin
5505024 bytes read in 233 ms (22.5 MiB/s)
=> startm7 0x80000000
Starting CM7_0 core at SRAM address 0x80000000 ... done.
=> go 0x80000000
## Starting application at 0x80000000 ...
"Synchronous Abort" handler, esr 0x02000000
elr: 0000000080000000 lr : 00000000ff8a8bc0 (reloc)
elr: 0000000080000000 lr : 00000000ff8a8bc0
x0 : 0000000000000001 x1 : 00000000ffc11cf8
x2 : 00000000ffc11cf8 x3 : 0000000000000001
x4 : 0000000000000000 x5 : 00000000ffbd3de5
x6 : 0000000000000030 x7 : 00000000ffbd4070
x8 : 0000000000000010 x9 : 0000000000000008
x10: 00000000ffffffd0 x11: 0000000000000010
x12: 0000000000000000 x13: 0000000000000200
x14: 000000000000000a x15: 0000000000000001
x16: 0000000080000000 x17: 0000000000000000
x18: 00000000ffbddd80 x19: 00000000ffc11cf8
x20: 0000000080000000 x21: 0000000000000002
x22: 00000000ffc11cf0 x23: 0000000000000002
x24: 00000000ff9654dc x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 00000000ffc11d50 x29: 00000000ffbd4070

Code: "Synchronous Abort" handler, esr 0x96000006
elr: 00000000ff8a2b1c lr : 00000000ff8a2afc (reloc)
elr: 00000000ff8a2b1c lr : 00000000ff8a2afc
x0 : 00000000ff930627 x1 : 0000000000000000
x2 : 00000000ff8f2c58 x3 : 0000000000000001
x4 : 00000000ffbd3c20 x5 : 00000000ffbd3c8b
x6 : 0000000000000030 x7 : 00000000ffbd3f10
x8 : 0000000000000001 x9 : 0000000000000008
x10: 00000000ffffffe8 x11: 0000000000000010
x12: 000000000001869f x13: 0000000000000200
x14: 000000000000000a x15: 0000000000000021
x16: 00000000ff8f26f0 x17: 0000000000000000
x18: 00000000ffbddd80 x19: 000000007ffffff0
x20: 00000000ff93839f x21: 00000000fffffffc
x22: 00000000ff93c21d x23: 00000000ff930627
x24: 00000000ff9654dc x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 00000000ffc11d50 x29: 00000000ffbd3f10

Code: d1004273 910876d6 aa0003f7 12800075 (b9400261)
Resetting CPU ...

resetting ...
NOTICE: Reset status: Destructive Reset (RUN)
NOTICE: BL2: v2.10.7(release):bsp43.0_rc5-2.10.7
NOTICE: BL2: Built : 08:17:37, Nov 26 2024


After the preceding commands are executed, the system resets
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