Hi NXP Experts,
I am currently working on the LIN implementation using the LLCE component on S32G3 (running as a LIN Master). We are using S32G_LLCE_1_0_10.
We have encountered a strange behavior regarding the Frame Timeout configuration in the LLCE LIN firmware, and I would like to seek some internal details or clarifications about the firmware's black-box logic.
Problem Description:
When configuring the LIN channel with "Disable Frame Timeout" UNCHECKED (meaning timeout detection is enabled) and setting the Response Timeout value to 14:
The LLCE LIN Master successfully transmits the Header (Break + Sync + PID) to the bus.
The Slave node receives the Header and responds with the correct Data + Checksum immediately.
However, the LLCE LIN Master randomly or constantly fails to capture/receive the data. It behaves as if the data is lost or dropped by the LLCE firmware.
Workaround Found:
If we simply CHECK "Disable Frame Timeout" (disabling the firmware's internal timeout logic) in the configuration tool while keeping all other hardware and physical bus environments exactly the same:
The Master never drops any data and successfully receives every single response from the Slave.
Our Questions:
Since the LLCE_firmware_user_guide.pdf provides very limited information about the internal state machine, we are confused by this behavior:
How is the timeout value "14" precisely calculated inside the LLCE firmware? Does a value of 14 represent absolute microseconds, bit times, or cycles related to a specific GPT/timer clock source?
Why does the Master fail to grab the response even when the Slave replies immediately? Is it possible that the timeout counter starts too early (e.g., before the Header finishes transmitting), or is "14" too small a threshold due to some internal hardware/firmware execution latency?
What is the recommended way to properly calculate and set this timeout value if we do want to keep the Frame Timeout protection active without dropping valid responses?
Any documentation, application notes, or insights into the LLCE LIN firmware's internal timing logic would be highly appreciated.
Thanks in advance!
Best regards,
cjq