S32G274 BSP39 DDR data bit interface swap

[jack_zhangjg]

Hi expert,

Our project using SOC S32G274 with BSP39.0 SDK.
We use the same SOC/DDR chip as officail S32G2-VNP-RDB2 board.
But the data bit of every Byte between SOC and DDR are swaped for conveniently layout.
For fast development, Could you please tell me which file/codes I need to modify in ATF, u-boot and kernel ?

Thanks.

[Daniel-Aguirre]

Hi,

We understand that all the required files should be generated under the DDR Tool inside S32 Design Studio for S32 Platforms. For generating the files, we can recommend looking into the AN12848 available under the S32G2 product page (link: S32G2 Safe and Secure Vehicle Network Processor | NXP Semiconductors). Once the files are generated, the BSP39.0 User Manual shows the next steps [Page 102, Chapter 11 DDR, BSP39.0 User Manual for S32G2 platforms, 12/2023] to correctly link the generated files into your build.

Please, let us know.

[jack_zhangjg]

Hi Daniel,
I'm using S32DS v3.5 windows version.
I follow the NXP doc, and do DDR training test.
In the configuration window(default DDR_CLK frequency 400Mhz), I just configure the "DQ Swapping" item following schematic diagram. I test several time, but all failed.

Could you please give me some advice?
I add DDR trainning failed log.

[Daniel-Aguirre]

Hi,

Thanks for your feedback. We understand that you are modifying the DQ lines and it is failing. Since we will require the schematic for the connections between your DDR and the S32G, help us opening a ticket under the NXP online services, for a private channel. Also, the capture of the DDR Tool Configuration will be required, for us to verify that the modifications are done as needed.

We do apologize.

Please let us know.

[jack_zhangjg · Accepted solution]

Hi Daniel,

Thank you for your reply.
This problem has been solved.
As the Revision of DDR chip we use is not the same as RDB2, although the chip model name is the same. 
We change the configuration of S32DS, and then DDR trainning Passed.

Thanks.