What's the correct sequence to reset the S32G2 and halt the cores before executing the first instruction?
The reference manual provides the following snippet, but this seems incomplete:
CM7_x_EDBGREQ alone does not seem to have the desired effect, the boot core (M7_0) starts executing normally. Also, the sequence doesn't include asserting a reset - shouldn't it include (for example) "assert functional reset" as one of the first steps?
Somewhat related:
How can I assert a destructive reset, and immediately keep the device in functional reset after the destructive reset?
If I assert both destructive reset and functional reset with MDM_AP CONTROL SYSRESETREQ & SYSFUNCRST, a destructive reset is executed. But both bits are cleared automatically and the device leaves reset state instead of staying in functional reset. I can set SYSFUNCRST again to assert functional reset, but then there's a brief period between destructive reset and functional reset where the device is out of reset.
Hi
Cores Cortex-M7_0, Cortex-M7_1, Cortex-M7_2, and Cortex-M7_HSE under main reset domain support debug and trace over Functional reset. you can referee High-level reset sequence flow , Destructive sequence flow diagram and Functional reset entry sequence flow diagram from reference manual. can also refer chapter 28-29 to understand reset in brief from reference manual.
can you provide information which debugger you are using and steps that you have performed. it will help up to debug issue.