Problem with S32G2 QSPI serial NOR micron flash sector erase command: SR.BUSY flag stuck

[SSyb]

ear all,

I am having headache with controlling a Micron MT35XU512ABA QSPI seial NOR flash from an S32G274A.
The board is a custom board (not one of the NXP RDB2 or EVP).
I run a classic AUTOSAR stack with the NXP Realtime-Driver Package SW32G_RTD_4.4_3.0.2_HF01 (but the differences to later versions are not so big), configured with the Tresos tool.

for the Fls driver configuzration, I started with the RDB2 example configuration provided by NXP in the "Integration_Reference_Examples_S32G2_2022_06" bundle and fom there
modified it to make it fit for the Micron MT35XU512ABA.
- otcal DDR mode
- register read, data read and page program/write work sucessfully

Problem: sector erase does not work

I am a newbie to QSPI flash, jumping from example to example. I still have not understood whether to send 1 or 2 CMD bytes for the erase LUT sequence:
- the Micron datasheet suggests there is noe CD byte, and 4 address bytes, and that's it.
- I have seen in other documents (e.g. the S32G_QSPINOR_定制_20211125_V3.pdf from the NXP website) that people use 2 CMD bytes in octal DDR mode, where one is the usual CMD code from the spec,  and the 2nd byte is a copy of the first one, or the the bit-inverted value. I have not read in any specification what is the background though.

What effects do I see:

(1) when I supply 1 cmd code plus address

8-8-0
instruction = CMD_DDR, opcode = 0xdc (erase 128 kB sector)
instruction = ADDRESS_DDR , opcode = 0x20 (4 bytes)

Result: Neither the QSPI IP SR.BUSY flag , nor the flash-internal status busy-flag are blocked for a noticeable duration, no errors returned from any involved RealtimeDriver API, but sector is not erased.
Finally Qspi_Ip_EraseVerify() fails (because the flash content is not equal flash erase values) -> sector erase not successfull

(2) when I supply 2 commands plus address
8-8-0
instruction = CMD_DDR, opcode = 0xdc (erase sector)
instruction = CMD_DDR, opcode = 0x23 (bit inverse version of 0xdc)
instruction = ADDRESS_DDR , opcode = 0x20 (4 bytes)

or
8-8-0
instruction = CMD_DDR, opcode = 0xdc (erase sector)
instruction = CMD_DDR, opcode = 0xdc (repeated erase sector)
instruction = ADDRESS_DDR , opcode = 0x20 (4 bytes)

Result: Right after submitting the LUT sequence from QWSPI controller to Flash the SR.BUSY flag of the S32G2 QSPI controller is set amd REMAINS set for a very long time.
(actually for some 2 seconds until my software hangs up because the process took too long).
The SR.AITF bit of the QSPI controller is also set.
However, after the next power-on reset, I see the sectors was actually erased sucessfully.

I am a little lost and have the following questions:

a) what is it with these 1-byte or 2-byte commands in otcal DDR mode ? is there a general rule that I have missed in some document ? in the Micron datasheet, I can't find
any hint to submit 2 bytes of CMD instruction, the command table lists only 1 byte for a command.

b) The SR.BUSY flag in the S32G2 QSPI controller: WHEN is this supposed to be reset ?
chapter 38.6.2.6 of the S32G2 Reference manual says:
"After the transaction is complete (all transmit and receive operations with the external serial flash memory device are
complete), the module resets SR[BUSY]. In case of an IP command, FR[TFF] is asserted."

Since the erase-sequence does not expect data in return, I understand that the SR.BUSY bit should be reset after transmitting the command to the flash, this should be finished in, say, nanoseconds.
(and not waiting for the actual sector erase inside the flash to finish).

c) and eventually: what is wrong with my erase sequence ?
Looks like the 2-byte sequence is the better direction, but do I really have to wait for the SR.BUSY flag until the sector is erased ...?

thanks and best regards,
Stefan

[Daniel-Aguirre]

Hi,

There is an Application Note (AN13563) which explains the creation of the different LUTs with the Macronix embedded Flash memory inside the RDB2 platform.

The OPI Sector Erase command on the Macronix part is defined as follows:

Which the 2nd CMD is the bit-inverted CMD you are seeing while on OPI mode. Have you taken a look into AN13563?

Please, let us know.

[SSyb]

Hi @Daniel-Aguirre , well everything works fine with the Macronix flash, but my problems occur with a Micron flash. The application notes that you mention I have read, but the examples are also w.r.t. the  Macronix flash found on the NXP reference boards.

My assumption is that the communication in octal DDR mode was not reliable, and that is why the busy bit was stuck, because the QSPI controller was waiting for something (some bits or signal edges) which did not come.

Since I did not find stable octal DDR parameters for the Micron flash, I have given up for the moment and stick with 1-1-1-SDR parameters. In this mode it works fine, no stuck BUSY bits (but everything slower of course).

I have to admit that even after reading the S32G2 reference manual, I have no clear understanding of the physical background of the QSPI latency and delay timing DLL (and I suspect the problem lies there). I am in touch now with the NXP FAE assigned to  my company, trying to find a solution for the long term.

-> problem worked-around, but not solved.

best regards, Stefan