PFE subsystem bring up on S32G2

[aaronbaranoff]

I am looking for a simple example of how to power up the PFE sub system and setting up the appropriate clocks. I have a driver that I have written that should work on a native A53 (no Linux).  The clocks never come up. I know that prior to me working on this logic I could not get the PFE registers to even read now they read but not everything is working and I have traced it down to this.

Here is the basic code to init the subsystem (this is very fragmented and not clearly explain by NXP) so any source example would be appreciated.

pfe_init(void)

{

    /* Enable */

    /* Setup DMA coherency */

    volatile uint32_t tries;

    RDC.RD2_CTRL_REG.B.RD2_CTRL_UNLOCK = 1;

    RDC.RD2_CTRL_REG.B.RD2_INTERCONNECT_INTERFACE_DISABLE = 0;

    tries = 0;

    while (RDC.RD2_STAT_REG.B.RD2_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT != 0 )

    {

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }

    }

    tries = 0;

    while (RDC.RD2_STAT_REG.B.RD2_INTERCONNECT_INTERFACE_DISABLE_STAT != 0)

    {

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }

    }

    /**((volatile unsigned int *)0x4007ca00) = 0x3f; */

    S32G_GPR.PFE_COH_EN.B.DDR = true;

    S32G_GPR.PFE_COH_EN.B.HIF0 = true;

    S32G_GPR.PFE_COH_EN.B.HIF1 = true;

    S32G_GPR.PFE_COH_EN.B.HIF2 = true;

    S32G_GPR.PFE_COH_EN.B.HIF3 = true;

    S32G_GPR.PFE_COH_EN.B.UTIL = true;

    /* Setup EMAC modes -RGMII (ALL PFES)*/

    S32G_GPR.PFE_EMACX_INTF_SEL.B.EMAC0 = 2;

    S32G_GPR.PFE_EMACX_INTF_SEL.B.EMAC1 = 2;

    S32G_GPR.PFE_EMACX_INTF_SEL.B.EMAC2 = 2;

    /* Enable power for PFE */

    S32G_GPR.PFE_PWR_CTRL.B.PWRACK = 0;

    S32G_GPR.PFE_PWR_CTRL.B.PWRCLAMP = 0;

    S32G_GPR.PFE_PWR_CTRL.B.PWRDWN = 0;

    S32G_GPR.PFE_PWR_CTRL.B.PWRISO = 0;

    S32G_GPR.GENCTRL1.B.CTRL = 1;

    /* Setup & Enable the PFE Sys Clock */

    /* Setup and Enable the PFE PE Clock */

    S32G_GPR.LLCE_CTRL.B.EXEVENT = 0;

    S32G_GPR.LLCE_CTRL.B.LINDIVSEL = 0;

    S32G_GPR.LLCE_CTRL.B.LLCE_HTM0_TRC_DIS = 0;

    S32G_GPR.LLCE_CTRL.B.LLCE_HTM1_TRC_DIS = 0;

    S32G_GPR.LLCE_CTRL.B.LLCE_LSPI_TRIG_IN = 0;

    S32G_GPR.LLCE_CTRL.B.PFE_2_LLCE_INT_HS_BP = 0;

    S32G_GPR.GENCTRL1.B.CTRL = 1;

    /* Setup EMAC Tx/RX clocks */

    S32G_GPR.GENCTRL0.B.ACCEL_FLXNC_RD0_IDLEREQ = 0; /* normal operation */

    S32G_GPR.GENCTRL0.B.ACCEL_FLXNC_REF_DIV = 0; /* Divide by 2 */

    S32G_GPR.GENCTRL0.B.USBPWRFLT = 0;    

    tries = 0;    

    do {

        MC_ME.PRTN2_COFB0_CLKEN.B.REQ0 = 1;

        MC_ME.PRTN2_COFB0_CLKEN.B.REQ1 = 1;

        MC_ME.PRTN2_COFB0_CLKEN.B.REQ2 = 1;

        MC_ME.PRTN2_COFB0_CLKEN.B.REQ3 = 1;

        Write_Control_Key();

        MC_ME.PRTN2_PCONF.B.OSSE = 1;

        MC_ME.PRTN2_PCONF.B.PCE = 1;

        MC_ME.PRTN2_PUPD.B.OSSUD = 1;

        MC_ME.PRTN2_PUPD.B.PCUD = 1;

        /* Tell hardware to check above registers for changes */

        Write_Control_Key();

        tries++;

        if (tries > MAX_TRIES)

        {

            break; /* code dies here - the clocks never get enabled
                      therefore it does not come out of reset */

        }

    } while (MC_ME.PRTN2_COFB0_STAT.R != 0xf);

    /* Put PFE in reset */

    MC_RGM.PRST_0[2].PRST_0.B.PERIPH_0_RST = 1;

    tries = 0;

    while (MC_RGM.PSTAT_0[2].PSTAT_0.B.PERIPH_0_STAT != 1)

    {

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }

    }    

    tries = 0;

    do {

        S32G_GPR.GENCTRL1.B.CTRL = 0;

        /* Take the PFE out of reset */

        MC_RGM.PRST_0[2].PRST_0.B.PERIPH_0_RST = 0;

        MC_ME.PRTN2_PCONF.B.OSSE = 1;

        MC_ME.PRTN2_PCONF.B.PCE = 1;

        MC_ME.PRTN2_PUPD.B.OSSUD = 1;

        MC_ME.PRTN2_PUPD.B.PCUD = 1;

        /* Tell hardware to check above registers for changes */

        Write_Control_Key();

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }

    } while (MC_RGM.PSTAT_0[2].PSTAT_0.B.PERIPH_0_STAT == 1);

    MC_ME.PRTN2_PCONF.B.OSSE = 0;

    MC_ME.PRTN2_PCONF.B.PCE = 1;

    MC_ME.PRTN2_PUPD.B.OSSUD = 1;

    MC_ME.PRTN2_PUPD.B.PCUD = 1;

    /* Tell hardware to check above registers for changes */

    Write_Control_Key();

    tries = 0;

    while (MC_RGM.PSTAT_0[2].PSTAT_0.B.PERIPH_0_STAT != 0)

    {

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }        

    }

}

[alejandro_e]

Hello @aaronbaranoff,

Thanks for the information, Please allow me some time to check those registers.

I will get back to you as soon as possible

[aaronbaranoff]

One more data point. I even tried putting the PFE_MAC2 in loopback (via the MAC_CONFIGURATION) register bit 12.  Still can't talk to those DMA related registers. 

[alejandro_e]

Hello @aaronbaranoff,

Here are the differences I found, same format as last time. For the MC_CGM_2 I stopped the program in the same line as last time, for the PFE_EMAC I stopped here:

alejandro_e_0-1762213117490.png

Let me know if the behavior is different after the changes. 

[aaronbaranoff]

I noticed a diff in values with the following location.

EL1N0xFFFF0000460A8800 you have a value of 0x00003FF7 the issue is that is not a documented register? What is it?

[aaronbaranoff]

I am confused or am I missing something. Our PFE setting I believe are close enough (MAC addresses, and other non-critical settings). But our CGM_2 settings are way off. Maybe the differs were captured on your side were before they were setup.

For PFE_MAC2 according to the documention (see images below).

CGM_2 Mux 0 needs to be set to 33 ACCEL_PLL_PH1_CLK (That we match)

CGM2 Mux 3 needs to be set to PERIPH_PLL_PHI5_CLK (I have that set but you are pointing to FIRC_CLK) 

CGM2 Mux 6 needs to be set to PFE_MAC2_RX_CLK(I have that set but you are pointing to FIRC_CLK) 

aaronbaranoff_3-1762261984775.png

aaronbaranoff_2-1762260652031.png

aaronbaranoff_0-1762260348653.png

[aaronbaranoff]

I addition can you dump and compare the register settings for the ACCEL_PLL per the documention we are setting it to 600 Mhz. 

Make sure the PFE_MAC_2 and the clocks are fully enabled prior to the compare. 

aaronbaranoff_0-1762266317144.png

aaronbaranoff_1-1762266376117.png

[aaronbaranoff]

After stating at you PFE configuration I realized it too was not fully initilalized. You had yet to write to the list addresses (or you can't)

0x00000000	EL1N:0xFFFF0000460A9114	00000000	0x00000000
0x00000000	EL1N:0xFFFF0000460A9118	00000000	0x00000000
0x00000000	EL1N:0xFFFF0000460A911C	00000000	0x00000000

[alejandro_e]

Hello @aaronbaranoff,

Sorry for the late reply,  here is the complete dump for all the PFE EMAC registers, from 0x460A8000-0x460A936C, you can check it with any hex viewer.

This dump was taken after finishing all initialization.

[aaronbaranoff]

Thank you for the dump.

When I compare your register settings and mine. I find you have no ring buffers or list addresses set up for any queues/channel.s How then are you sending packets? Clearly not the documented DMA interface. Is that inteface disabled on the PFE MACs? If so how do I send packets?

[alejandro_e]

Hello @aaronbaranoff,

I took the dump just before sending any frames, to show the PFE registers configuration.

To know exactly how to send packages using PFE, I strongly recommend you check the PFE MCAL API, in particular, check the function calls starting from example_application\src\sample_app_ethswt_eth.c, in Tst_Pfe_SendDummyFrame() there is a call to the API Eth_43_PFE_Transmit(), the MCAL code includes a lot of runtime and compilation checks that may not be useful to you, you can strip the code as you require, however that is the best reference on how to use the PFE send functionality.

Thanks

[aaronbaranoff]

Do you have any documnetion on HIF particularly the ring buffer structure and the registers?

On a seperate not so I can get it transmitting nad recieving packets without the complexities. How do I transmit and recived via the DEBUG FIFO interface in the MTL. 

[alejandro_e]

Hello @aaronbaranoff,

We do not have any specific documentation regarding the  HIF and its ring buffers. To this point I have already shared all documentation regarding the PFE, there is no more documents we have on that. That said, you can check section 2.1 Network Interfaces of the LNX PFE Driver User Manual or section 11.5.2 Configuration example and 11.7 Egress QoS of the PFE FCI API Reference.

Regarding the Tx and Rx of packets 'without the complexities', I'm afraid that there is no way to avoid the PFE complexities if you want to take advantage of it, if you prefer you can use the GMAC module, which is quite simpler, however you will need to handle all the operations in the main core.

[alejandro_e]

Hello @aaronbaranoff,

 Thanks for all the info. I tried testing the PFE Demo application, however with the S32 Debug Probe I have encountered some problems that lead to a hard fault. I will need to test this with a Lauterbach debugger, as suggested in the description the demo app. However, I do not have one with me at this exact time, I will need to get one next week and perform the tests.

Regards the call, me and my team do not handle calls with customer, moreover, it usually takes me quite some time to find relevant information for a reply.

Sorry for the delay on the relevant reply.