PFE interface

[JasonTseng]

Hello,

Please check p. 15 from below link

https://www.nxp.com/design/training/understanding-the-s32g2-ethernet-architecture:TIP-UNDERSTANDING-...

It said " Total of 7 available data interfaces
4x host
...
SGMII: 1 Gbps, 100 Mbps, PFE_MAC0 also 2.5 Gbps"

Q1: The number of hosts (hif 0 - hif3) are only 4 and restricted by 4, is it software defined or hardware limitation? any further details about it?

Q2: how do these hif map to arm core (as we know there are many A53 and M7 cores)?

for example a traffic from pfe_mac0 goes to pfe then go to hif1 then go to cpu2 ???

Q3: this ppt is talking about S32G2, how about S32G3? does S32G3 also have the same configuration?

i.e 7 interfaces, 4 hosts, 3 pfe_mac?

Thanks

[JasonTseng]

I think I knew the answers.

However, follow up question2, it should be flexible to link certain hif to any of arm cores.

Please advise how to configure it in details.

Thanks

[brian14]

Hi @JasonTseng, 

Thank you for contacting NXP Support!

Please have a look to S32G2 Reference Manual (S32G2 Safe and Secure Vehicle Network Processor | NXP Semiconductors), specifically the section "Packet Forwarding Engine". Here you will find the official description of this interface such as programming considerations and functional descriptions.